FPGA-based packets processing acceleration platform for VNF
FPGA-based packets processing acceleration platform for VNF
复制标题
基于 FPGA 的 VNF 数据包处理加速平台
DOI:
10.1109/icsess.2017.8342922
复制
发表时间:
2017
期刊:
影响因子:
--
通讯作者:
Julong Lan
中科院分区:
文献类型:
--
作者:
Tianyi Lan;Qing Han;Hongwei Fan;Julong Lan
While there has been a belief over the past few years that virtual network functions (VNFs) should be built on common servers, we argue that it can lead to limited performance and large up/down traffic. This paper proposes a new idea of shifting part of NFV functions from software packages to common hardware devices to promote overall performance. Then we present the design and implementation of PPAP, a Packets Processing Acceleration Platform for NFV. It offers high flexibility by allowing functions to control the processing flow of hardware. Dynamic match tables and virtualization techniques ensure isolation among VNF instances.