Deep Understanding of Negative Gate Voltage Restriction for SiC mosfet Under Wide Temperature Range
Deep Understanding of Negative Gate Voltage Restriction for SiC mosfet Under Wide Temperature Range
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DOI：
10.1109/tpel.2021.3056435
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发表时间：
2021-02
影响因子：
6.7
通讯作者：
Ximing Chen;Xuan Li;Bangbing Shi;Junmiao Xiang;Yuan-Tung Dai;Chenzhan Li;Xiaochuan Deng;H. Luo
中科院分区：
文献类型：
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作者：
Ximing Chen;Xuan Li;Bangbing Shi;Junmiao Xiang;Yuan-Tung Dai;Chenzhan Li;Xiaochuan Deng;H. Luo
通过将碳化硅(SIC)金属氧化物半导体场效应晶体管(MOSFET)的MOS栅极结构分成N型JFET和P型沟道区，在相同的制造工艺和热预算下，深入揭示了不同VGS和高温(高达300℃)下栅极可靠性问题的根源和相关的物理见解。在25~300℃温度范围内，SiCMOSFET的正VGS安全极限主要取决于JFET表面的栅氧化层，而负VGS的安全极限主要取决于沟道表面的栅氧化层。沟道表面的栅氧化层在Fowler-Nordheim(F-N)隧穿方面弱于JFET表面的栅氧化层，导致了当前的SiCMOSFET的安全VGS不对称。此外，当温度在25~150℃时，−15V<；Vgs<；25V下栅氧化层的退化是由空穴或电子直接隧穿机制引起的。然而，当温度达到300C时，−5V<；Vgs<；10V下栅氧化层的退化是由空穴或电子跳跃导电机制引起的。此外，还通过随时间变化的介质击穿测量来评估栅氧化层的可靠性。栅氧化层的电荷击穿(QBD)在300℃时严重退化，这主要是由于势垒高度({it{\Phi}}{\rMB}$)退化所致。这些工作可在较高VGS偏置(特别是负偏压)和较高温度(300°C)下为SiCMOSFET提供准确的栅氧化层弱点，从而进一步帮助使用和设计具有SiCMOSFET快速操作的坚固耐用的转换器。
In this letter, the origin and related physical insights of gate reliability issues under various Vgs and high temperatures (up to 300 °C) are revealed in-depth, through splitting MOS gate structure of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) into N-type JFET and P-type channel region under identical manufacturing processes and thermal budgets of SiC MOSFETs. From 25 to 300 °C, the safety limit of positive Vgs of SiC MOSFETs is mainly dependent on the gate oxide on the JFET surface, whereas that of negative Vgs is dependent on the gate oxide on the channel surface. The gate oxide on the channel surface is weaker than that on the JFET surface in terms of Fowler–Nordheim (F-N) tunneling, resulting in asymmetric safety Vgs of current SiC MOSFET. Moreover, when temperature ranges from 25 to 150 °C, the degradation of gate oxide under −15 V < Vgs < 25 V is caused by the hole or electron direct tunneling mechanism. However, when the temperature reaches 300 °C, the degradation of gate oxide under −5 V < Vgs < 10 V is caused by the hole or electron hopping conduction mechanism. Furthermore, the reliability of gate oxide is evaluated by the time-dependent dielectric breakdown measurement. The charge-to-breakdown (QBD) of gate oxide is severely degraded at 300 °C mainly due to the barrier height (${\it{ \Phi}}_{\rm B}$) degradation. These efforts can provide accurate weakness points of gate oxide under higher Vgs bias (particular for negative bias) and higher temperature (300 °C) for SiC MOSFETs, further helping use and design rugged converters with the fast-speed operation of SiC MOSFETs.