An area efficient 128 channel counter chip
An area efficient 128 channel counter chip
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面积高效的 128 通道计数器芯片
DOI：
10.1016/0168-9002(96)00200-8
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发表时间：
1996
影响因子：
1.4
通讯作者：
P. Fischer
中科院分区：
文献类型：
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作者：
P. Fischer
N位长度的移位寄存器可以(对于大多数N位)配置为单个异或门，以周期性地生成2N−1不同状态。由于每个状态与接收到的时钟脉冲的数量直接相关，因此这样的电路可以用作计数器。位模式的顺序读出几乎不需要额外的逻辑，并且在多通道系统中，在读出期间可以很容易地以菊花链形式连接许多“移位计数器”。由于结构简单，可以实现非常规则和紧凑的布局。该电路的最大时钟频率很高(在2.4μm工艺中高于50 MHz)，并且与长度无关。设计并测试了一种128通道定标器芯片，用于波恩-康普顿偏振仪，利用硅条探测器快速测量光束轮廓。这一概念的其他可能应用是用于微带和像素探测器的专用读出芯片。
A shift register of N bit length can be configured (for most N) with a single exclusive-OR gate to generate periodically 2N− 1 different states. As each state is directly related to the number of clock pulses received, such a circuit can be used as a counter. The sequential readout of the bit pattern requires nearly no additional logic and many “shift counters” can easily be daisy chained during readout in a multichannel system. A very regular and compact layout is possible due to the simple structure. The maximum clocking frequency of the circuit is high (above 50 MHz in a 2.4 μm process) and independent of the length. A 128 channel scaler chip has been designed and tested to be used in the Bonn Compton polarimeter for a fast measurement of beam profiles with silicon strip detectors. Other possible applications of this concept are specialized readout chips for microstrip and pixel detectors.