Three-Dimensional Layout of On-Chip Tree-Based Networks
Three-Dimensional Layout of On-Chip Tree-Based Networks
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DOI：
10.1109/i-span.2008.39
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发表时间：
2008-05
期刊：
影响因子：
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通讯作者：
Hiroki Matsutani;M. Koibuchi;D. Hsu;H. Amano
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文献类型：
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作者：
Hiroki Matsutani;M. Koibuchi;D. Hsu;H. Amano
三维片上网络（3-D NoC）是一个新兴的研究领域，探索3-D集成电路的网络架构，将几个较小的晶圆或骰子堆叠在一起，以减少导线长度和导线延迟。各种网络拓扑结构，如网格、环面和树已被用于noc。特别是，许多注意力集中在基于树的拓扑结构上，如胖树和胖h树，因为与网格或环面相比，它们的跳数相对较短，可以实现更低的延迟通信。然而，由于片上树型网络的二维布局在根周围有很长的导线连接，它们会产生严重的导线延迟，给现代VLSI设计带来严重的问题。为了解决三维集成电路树的固有缺点，本文提出了一种包括胖树和胖h树在内的树的三维布局方案。从网络逻辑面积、线长、线延迟、中继器插入数、能耗等方面对三维布局与二维布局进行了比较。评价结果表明：1)总钢丝长度减少25.0% ~ 50.0%；2)改善了线延迟，消除了消耗大量能量的中继器缓冲器；3)飞行传输能量降低高达47.0%；4)面积开销最多为7.8%，这与3d网格和环面相比是有利的。
Three-dimensional network-on-chip (3-D NoC) is an emerging research area exploring the network architecture of 3-D ICs that stack several smaller wafers or dice for reducing wire length and wire delay. Various network topologies such as meshes, tori, and trees have been used for NoCs. In particular, much attention has been focused on tree-based topologies, such as fat trees and fat H-tree, because of their relatively short hop-count that enables lower latency communication compared to meshes or tori. However, since on-chip tree-based networks in their 2-D layouts have long wire links around the root, they generate serious wire delay, posing severe problems to modem VLSI design. In this paper, we propose a 3-D layout scheme of trees including Fat Trees and fat H-tree for 3-D ICs in order to resolve the trees' intrinsic disadvantage. The 3-D layouts are compared with the original 2-D layouts in terms of network logic area, wire length, wire delay, number of repeaters inserted, and energy consumption. Evaluation results show that 1) total wire length is reduced by 25.0% to 50.0%; 2) wire delay is improved and repeater buffers that consume considerable energy can be removed; 3) flit transmission energy is reduced by up to 47.0%; 4) area overhead is at most 7.8%, which compares favorably to those for 3-D mesh and torus.