High-k gate stack on GaAs and InGaAs using in situ passivation with amorphous silicon
High-k gate stack on GaAs and InGaAs using in situ passivation with amorphous silicon
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DOI：
10.1016/j.mseb.2006.08.018
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发表时间：
2006-12-15
期刊：
影响因子：
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通讯作者：
Lee, J. C.
中科院分区：
文献类型：
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作者：
Oktyabrsky, S.;Tokranov, V.;Lee, J. C.
为了降低界面态密度，避免在III-V-High-k界面处发生费米能级钉扎，我们在分子束外延生长的GaAsMOSFET沟道上原位沉积了一层非晶硅界面钝化层(a-SiIPL)。用HfO2介质和TaN金属栅在IPL顶部异地制作了高k栅堆栈。采用透射电子显微镜、X射线光电子能谱和电容-电压法相结合的方法，研究了不同IPL厚度样品的界面结构及其化学组成与界面态形成/钝化的关系。当SiIPL被部分氧化时，在GaAs片和InGaAs片上都显示出非钉扎费米能级，对应于a-SiIPL的最小厚度为1.5um。栅极堆叠的热稳定性高达750℃，适合于MOSFET工艺中的硅离子注入激活。耗尽型和增强型n沟道MOSFET的跨导均为0.27 ms/mm，沟道长度为100µm，沟道电子迁移率高达1100 cm(2)/V S。(C)2006 Elsevier B.V.版权所有。
To reduce density of interface states and avoid Fermi level pinning at the III-V-high-k interface we employed an amorphous Si interface passivation layer (a-Si IPL) in situ deposited on top of GaAs or InGaAs MOSFET channels grown by molecular beam epitaxy. The high-k gate stack was further fabricated ex situ on top of the IPL with HfO2 dielectric and TaN metal gate. Combination of transmission electron microscopy, X-ray photoelectron spectroscopy and capacitance-voltage methods was applied to the samples with various IPL thicknesses to study correlations of the interface structure and its chemistry with the formation/passivation of interface states. An unpinned Fermi level is demonstrated on both GaAs and InGaAs wafers when Si IPL is partially oxidized, corresponding to the minimum thickness of the a-Si IPL of 1.5 um. Thermal stability of the gate stack up to 750 degrees C was demonstrated, making it appropriate for Si implant activation within MOSFET technology. Both depletion mode and enhancement mode n-channel MOSFETs were demonstrated with transconductance 0.27 mS/mm for 100 mu m-long channel and channel electron mobility as high as 1100 cm(2)/V S. (c) 2006 Elsevier B.V. All rights reserved.