Rapid prototyping of a fixed-complexity sphere decoder and its application to iterative decoding of turbo-MIMO systems
Rapid prototyping of a fixed-complexity sphere decoder and its application to iterative decoding of turbo-MIMO systems
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固定复杂度球形解码器的快速原型设计及其在 Turbo-MIMO 系统迭代解码中的应用
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发表时间：
2007
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通讯作者：
L. Linan
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作者：
L. Linan
无线通信是电信最快增长的部分之一，其应用程序从语音通信到高速互联网访问。此外，正在研究新标准，以扩大无线通信的可能性，例如第四代细胞（4G）和超宽带（UWB）系统。近年来，在发射器和接收器上使用多个天线（也称为多重输入式输出（MIMO））已成为无线通信的新边界，与单纳特纳相比，链接质量或数据速率提高了。系统。该论文集中于对MIMO检测的球体解码器（SD）的分析。与最大似然检测器（MLD）相比，它提供了最佳的最大似然性（ML）性能，并具有降低的复杂性。但是，由于其可变的复杂性和树搜索的顺序性质，该算法的现场编程门阵列（FPGA）实现了几个缺点。结果表明，鉴于该算法无法完全管道，其实现会导致对硬件资源的次数使用。此外，它具有可变的吞吐量（即可以检测到每秒的位数），将其集成到完整的通信系统中，在该系统中需要在固定数量的操作中处理数据。这项研究提出了一个固定复合体球解码器（FSD）来克服SD的缺点。它提供了固定的复杂性，并实现了准最大可能性（ML）性能，从而通过一小部分传输星座与新通道矩阵排序相结合了搜索。与文献中SD的大多数优化相比，这是一种新颖的方法，该方法集中在降低算法的平均复杂性上。结果，与以前的SD硬件实现相比，使用较少的FPGA资源使用FPGA资源提供了相同的错误性能，并实现了相同的错误性能，并实现了相同的错误性能。相同的FSD概念应用于链路两端和64个二次振幅调制（QAM）的大型MIMO系统。对于该大小的系统，如果要实现ML性能，则是第一种实时获得准ML性能的方法。在当前的无线通信系统中，应用了某种形式的外通道编码以提高系统的可靠性。在这种情况下，MIMO检测器需要提供软价信息，以便使用涡轮原理进行迭代检测和解码。因此，提出了FSD（LFSD）的列表扩展名，以获取有关编码位的软值信息。 LFSD结合了相同的通道矩阵排序和扩展的固定搜索，以生成用于软价计算的候选列表。根据扩展搜索的大小，可以实现不同级别的性能和复杂性，使该算法适合于可重构体系结构。它的FPGA实现显示了如何使用完全管道的体系结构获得软价信息。它提供了一个恒定的吞吐量，该吞吐量比以前呈现的软莫莫检测器实现高得多。原创宣言我在此宣布，本文记录的研究和论文本身是由我本人组成的，完全由我本人撰写在爱丁堡大学工程和电子学院的数字通信研究所中。用于执行模拟的软件完全由我自己编写
Wireless communications is one of the most rapidly growing segments of telecommunications with applications ranging from voice communication to high-speed internet access. In addition, new standards are being investigated to broaden the possibilities of wireless communications such as fourth generation cellular (4G) and ultra-wideband (UWB) systems. In recent years, the use of multiple antennas at both transmitter and receiver, also known as multiple inputmultiple output (MIMO), has become the new frontier of wireless communications, increasing the quality of the link or the data-rate compared to single-antenna systems. This thesis concentrates on the analysis of the sphere decoder (SD) for MIMO detection. It provides optimal maximum likelihood (ML) performance with reduced complexity compared to the maximum likelihood detector (MLD). However, a field-programmable gate array (FPGA) implementation of the algorithm presents several disadvantages due to its variable complexity and the sequential nature of its tree search. It is shown that its implementation results in a sub-optimum use of the hardware resources given that the algorithm cannot be fully pipelined. In addition, it has a variable throughput (i.e. number of bits that can be detected per second) jeopardizing its integration into a complete communication system, where data needs to be processed in a fixed number of operations. This research proposes a fixed-complexity sphere decoder (FSD) to overcome the drawbacks of the SD. It provides a fixed complexity and achieves quasi-maximum likelihood (ML) performance, combining a search through a small subset of the transmitted constellation with a novel channel matrix ordering. This represents a novel approach compared to most optimizations of the SD in the literature, which concentrate on reducing the average complexity of the algorithm. As a result, an implementation of the FSD is shown to provide the same error performance using less FPGA resources and achieving a considerably higher (and constant) throughput compared to previous SD hardware implementations. The same FSD concept is applied to a large MIMO system with 4 antennas at both ends of the link and 64-quadrature amplitude modulation (QAM). It represents the first approach to obtain quasi-ML performance in real-time for a system of that size, previously thought to require a detector with prohibitive complexity if ML performance was to be achieved. In current wireless communication systems, some form of outer channel coding is applied in order to improve the reliability of the system. In that case, the MIMO detector needs to provide soft-value information in order to perform iterative detection and decoding using the turbo principle. For that reason, a list extension of the FSD (LFSD) is proposed to obtain soft-value information about the coded bits. The LFSD combines the same channel matrix ordering and an extended fixed search to generate a list of candidates for soft-value calculation. Depending on the size of the extended search, different levels of performance and complexity can be achieved making the algorithm suitable for reconfigurable architectures. Its FPGA implementation shows how soft-value information can be obtained with a fully pipelined architecture. It provides a constant throughput which is considerably higher than previously presented softMIMO detector implementations. Declaration of Originality I hereby declare that the research recorded in this thesis and the thesis itself was composed and originated entirely by myself in the Institute for Digital Communications, School of Engineering and Electronics at The University of Edinburgh. The software used to perform the simulations was written entirely by myself with the following