A Novel SiC MOSFET With Embedded Auto-Adjust JFET With Improved Short Circuit Performance
A Novel SiC MOSFET With Embedded Auto-Adjust JFET With Improved Short Circuit Performance
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DOI：
10.1109/led.2021.3124526
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发表时间：
2021-12-01
影响因子：
4.9
通讯作者：
Zhang, Bo
中科院分区：
文献类型：
--
作者：
Li, Xu;Deng, Xiaochuan;Zhang, Bo
在这封信中，提出了一种具有嵌入式自动调节常开 JFET (ADJ-MOSFET) 的新型平面栅极 SiC MOSFET，并对其进行了表征，以提高短路能力。常开自动调节 JFET (AD-JFET) 嵌入 P 阱区，作为电子从 N 型源极到 SiC MOSFET 沟道区的传导路径。同时，器件的P型源极分裂为两部分，其中一部分作为AD-JFET的栅极。在高直流总线电压（短路）条件下，AD-JFET 的有效沟道宽度将因耗尽电荷的增加而减小。因此，AD-JFET沟道的势垒会迅速增大，导致电子传输变得困难。 AD-JFET 的势垒会根据漂移区 JFET 区域的势垒自动调整，从而减少 SiC MOSFET 较高势垒引起的饱和（峰值短路）电流。与传统平面栅SiC MOSFET相比，ADJ-MOSFET不仅降低了33%的峰值短路电流，而且在800 V直流母线电压下的短路承受时间从8 μs增加到14 μs。此外，还为 SiC ADJ-MOSFET 提出了一种自动调节 JFET 势垒模型。
In this letter, a novel planar gate SiC MOSFET with embedded auto-adjust normally-on JFET (ADJ-MOSFET) is proposed and characterized to improve short circuit capability. The normally-on auto-adjust JFET (AD-JFET) is embedded in P-well region as the conduction path of electrons from N-type source to the channel region of SiC MOSFET. Meanwhile, the P-type source of device splits into two parts, one of which serves as the gate of AD-JFET. Under high DC bus voltage (short circuit) conditions, the effective channel width of AD-JFET will be reduced by the increased depletion charge. Therefore, the potential barrier of AD-JFET channel will increase rapidly, making it difficult for electrons transporting. The potential barrier of AD-JFET will be adjusted by that of the JFET region in drift region automatically, resulting in a reduction of the saturation (peak short circuit) current caused by the higher potential barrier of SiC MOSFET. Compared with conventional planar gate SiC MOSFET, ADJ-MOSFET not only reduces 33% peak short circuit current, but also increases short circuit withstanding time from 8 mu s to 14 mu s under 800 V DC bus voltage. Furthermore, an auto-adjust JFET barrier model is proposed for SiC ADJ-MOSFET.