An All-Digital Fully Integrated Inductive Buck Regulator With A 250-MHz Multi-Sampled Compensator and a Lightweight Auto-Tuner in 130-nm CMOS
An All-Digital Fully Integrated Inductive Buck Regulator With A 250-MHz Multi-Sampled Compensator and a Lightweight Auto-Tuner in 130-nm CMOS
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DOI：
10.1109/jssc.2017.2693243
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发表时间：
2017-06
影响因子：
5.4
通讯作者：
Monodeep Kar;Arvind Singh;Anand Rajan;V. De;S. Mukhopadhyay
中科院分区：
文献类型：
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作者：
Monodeep Kar;Arvind Singh;Anand Rajan;V. De;S. Mukhopadhyay
一个125 MHz的完全集成电感降压稳压器，使用11.6 nH的引线键合电感和3.2 nF的片上电容是在130 nm CMOS。提出了一种全数字架构，以简化数字过程节点中的集成。IVR演示了通过降低精度计算的多采样数字补偿器实现的增强带宽。提出了一种快速、轻量的自整定发动机，以优化无源元件变化下的稳态稳定性和瞬态响应。提出了一种阻性瞬态辅助方案和一种自适应全数字不连续导通模式控制，分别用于减少瞬态响应时间和提高轻载效率。该130 nm测试芯片的峰值效率为71%，在大参考瞬态期间的输出压摆为2.9 V/ $\mu \text{s}$。
A 125-MHz fully integrated inductive buck voltage regulator using 11.6-nH wirebond inductance and 3.2-nF on-chip capacitance is presented in 130-nm CMOS. An all-digital architecture is presented to ease integration in digital process nodes. The IVR demonstrates enhanced bandwidth enabled by a multi-sampled digital compensator with reduced precision computation. A fast and lightweight auto-tuning engine is presented to optimize steady-state stability and transient response under variation in passives. A resistive transient assist scheme and an adaptive all-digital discontinuous conduction mode control are presented to reduce transient response time and enhance light-load efficiency, respectively. The 130-nm testchip demonstrates a peak efficiency of 71% and a 2.9-V/ $\mu \text{s}$ output slew during large reference transient.