A Real-Time High-Throughput LDPC Decoder for IEEE 802.3an Standard
A Real-Time High-Throughput LDPC Decoder for IEEE 802.3an Standard
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适用于 IEEE 802.3an 标准的实时高吞吐量 LDPC 解码器
DOI：
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发表时间：
2010
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通讯作者：
Sau
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文献类型：
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作者：
Jui;Li;Sau
由于良好的误码率性能，现有的LDPC解码器大多基于置信传播（BP）算法。然而，它们需要大的芯片面积。针对IEEE 802.3an标准中采用的(2048, 1723) RS-LDPC码，本文提出了一种基于位翻转算法的高吞吐量LDPC解码器。通过引入翻转低相关位的策略和附加校正子投票方案，实现了高解码性能和低迭代次数。因此，解码性能非常接近最流行的基于 BP 的最小和算法 (MSA)，但计算复杂度却低得多。此外，该解码器具有较高的硬件利用率和实时处理能力。采用UMC 90nm工艺合成，在500MHz时钟速率下，解码器芯片面积、吞吐量和平均功耗分别为1.42M门、16Gbps和368mW。与现有的基于BP的设计相比，它具有更小的芯片面积和更低的功耗，并且性能相当。
The existing LDPC decoders are mostly based on the belief-propagation (BP) algorithms, due to good BER performances. However, they demand large chip areas. This paper proposes a high-throughput LDPC decoder based on the bit-flipping algorithms, for the (2048, 1723) RS-LDPC code adopted in the IEEE 802.3an standard. High decoding performances and low iteration numbers are achieved by introducing a strategy of flipping low-correlation bits and an additional syndrome vote scheme. As a result, the decoding performance is very close to the most popular BP-based min-sum algorithm (MSA) but with much lower computational complexity. Besides, the decoder achieves high hardware utilization with real-time processing capability. Synthesized with UMC 90nm process, the decoder chip area, throughput and average power dissipation are 1.42M gates, 16Gbps and 368mW, respectively, at 500MHz clock rate. Compared with existing BP-based designs, it has much smaller chip area and lower power dissipation, with comparable performances.