DSAGEN: Synthesizing Programmable Spatial Accelerators
DSAGEN: Synthesizing Programmable Spatial Accelerators
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DOI：
10.1109/isca45697.2020.00032
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发表时间：
2020-05
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通讯作者：
Jian Weng;Sihao Liu;Vidushi Dadu;Zhengrong Wang;Preyas Shah;Tony Nowatzki
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作者：
Jian Weng;Sihao Liu;Vidushi Dadu;Zhengrong Wang;Preyas Shah;Tony Nowatzki
与通用处理器相比，特定领域的硬件加速器可以提供数量级的加速和能源效率。然而，它们在硬件设计和软件堆栈开发中需要大量的手工工作。自动生成ASIC(例如；HLS)可能不够，因为硬件变得不灵活。理想的加速器生成框架应该是可自动化的，支持对领域的深度专门化，并维护统一的编程接口。我们的见解是，许多先前的加速器架构可以通过组合少量硬件原语来近似，特别是那些来自空间架构的原语。通过仔细的设计，编译器可以理解如何使用可用的原语，以及模块化和可组合的转换，以利用给定程序的特性。这暗示了一种范例，在这种范例中，加速器可以通过在如此丰富的加速器设计空间中进行搜索来生成，并受硬件原语及其交互的输入程序的亲缘性的指导。我们使用这种方法来开发DSAGEN框架，该框架使可重构加速器的硬件/软件协同设计过程自动化。对于几个现有的加速器，我们的评估表明编译器可以达到手动调优版本的89%的性能。对于自动化设计空间探索，我们针对先前加速器设计的多组工作负载；生成的硬件比以前的可编程加速器平均具有1.3× perf2/mm2。
Domain-specific hardware accelerators can provide orders of magnitude speedup and energy efficiency over general purpose processors. However, they require extensive manual effort in hardware design and software stack development. Automated ASIC generation (eg. HLS) can be insufficient, because the hardware becomes inflexible. An ideal accelerator generation framework would be automatable, enable deep specialization to the domain, and maintain a uniform programming interface. Our insight is that many prior accelerator architectures can be approximated by composing a small number of hardware primitives, specifically those from spatial architectures. With careful design, a compiler can understand how to use available primitives, with modular and composable transformations, to take advantage of the features of a given program. This suggests a paradigm where accelerators can be generated by searching within such a rich accelerator design space, guided by the affinity of input programs for hardware primitives and their interactions. We use this approach to develop the DSAGEN framework, which automates the hardware/software co-design process for reconfigurable accelerators. For several existing accelerators, our evaluation demonstrates that the compiler can achieve 89% of the performance of manually tuned versions. For automated design space exploration, we target multiple sets of workloads which prior accelerators are design for; the generated hardware has mean 1.3× perf2/mm2 over prior programmable accelerators.