Universal trench design method for a high-voltage SOI trench LDMOS
Universal trench design method for a high-voltage SOI trench LDMOS
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DOI：
10.1088/1674-4926/33/7/074006
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发表时间：
2012
影响因子：
5.1
通讯作者：
X. Hu 胡;B. Zhang 张;X. Luo 罗;Z. Li 李
中科院分区：
文献类型：
--
作者：
X. Hu 胡;B. Zhang 张;X. Luo 罗;Z. Li 李
介绍了一种高压SOI沟槽LDMOS的设计方法，该LDMOS具有不同的沟槽电阻率、宽度和深度。首次提出了一种有效设计的通用方法，考虑了击穿电压（BV）和比导通电阻（Rs，on）之间的权衡。高k（相对介电常数）电介质适合于填充浅且宽的沟槽，而低k电介质适合于填充深且窄的沟槽。本文还讨论了在漂移区引入真空沟槽的SOI LDMOS。模拟结果表明，由于其缩短的单元间距，可以用填充有低k电介质的沟槽来实现高FOM BV 2/Rs，on。
The design method for a high-voltage SOI trench LDMOS for various trench permittivities, widths and depths is introduced. A universal method for efficient design is presented for the first time, taking the trade-off between breakdown voltage (BV) and specific on-resistance (Rs,on) into account. The high-k (relative permittivity) dielectric is suitable to fill a shallow and wide trench while the low-k dielectric is suitable to fill a deep and narrow trench. An SOI LDMOS with a vacuum trench in the drift region is also discussed. Simulation results show that the high FOM BV2/Rs,on can be achieved with a trench filled with the low-k dielectric due to its shortened cell-pitch.