Low-Power CMOS Equalizer Design for 20-Gb/s Systems
Low-Power CMOS Equalizer Design for 20-Gb/s Systems
复制标题
适用于 20 Gb/s 系统的低功耗 CMOS 均衡器设计
DOI：
10.1109/jssc.2011.2134450
复制
发表时间：
2011
影响因子：
5.4
通讯作者：
B. Razavi
中科院分区：
文献类型：
--
作者：
S. Ibrahim;B. Razavi
随着引脚数和数据速率的增加，有线电路的功耗变得越来越重要。本文描述了一种用于决策反馈均衡器（dfe）的功率缩放方法和一种新的半速率推测架构，以缓解速度-功率权衡。采用90纳米CMOS技术设计的20 gb /s原型由线性均衡器和一抽头DFE组成，补偿了18英寸FR4走线的损失，同时从1 v电源输出40 mW。
The power consumption of wireline circuits has become increasingly more critical as the pin count and data rate rise. This paper describes a power scaling methodology and a new half-rate speculative architecture for decision-feedback equalizers (DFEs) to relax the speed-power trade-offs. Designed in 90-nm CMOS technology, a 20-Gb/s prototype consisting of a linear equalizer and a one-tap DFE compensates for the loss of an 18-in FR4 trace while drawing 40 mW from a 1-V supply.