Fast, layout-aware validation of test-vectors for nanometer-related timing failures
Fast, layout-aware validation of test-vectors for nanometer-related timing failures
复制标题
对纳米相关时序故障的测试向量进行快速、布局感知的验证
DOI：
10.1109/icvd.2004.1260984
复制
发表时间：
2004
期刊：
影响因子：
--
通讯作者：
C. Ravikumar
中科院分区：
文献类型：
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作者：
A. Kokrady;C. Ravikumar
ATPG工具生成测试向量假设零延迟模型的逻辑门。然而，实际上，栅极具有有限的上升和下降延迟，其取决于晶片上和管芯内的不同管芯上的工艺、电压和温度变化。测试工程师必须在将矢量移交给产品工程师之前验证矢量的时序正确性。目前，测试向量的验证是通过使用测试向量对电路进行动态仿真来完成的。如果在测试设备的信号放置和观察误差窗口下，测试矢量不能可靠地区分好电路和故障电路，则测试矢量无效。随着芯片的速度越来越快，人们已经认识到需要以预期的运行速度对其进行测试;因此，全速功能测试，存储器BIST和转换延迟测试正在用于现代ASIC。由于结构测试可能会导致电路中的开关活动比正常工作期间的估计要多得多，因此它们可能会因串扰和IR压降等纳米效应而无法通过延迟测试。因此，由动态模拟执行的验证可能容易出错。这里是一个测试的情况下，过度行使的芯片，并宣布它有故障，即使芯片可以正确地工作在功能模式下，在预期的速度。这个问题的一个解决方案是过度设计，例如使电源轨尺寸过大或增加布线间距，但这将影响产品的产量。我们提出了布局感知验证的速度测试向量和消除测试向量，可能会导致错误分类。试图在动态仿真中解决这种验证问题将迫使使用电路仿真或混合级仿真技术，这些技术在运行时间方面是昂贵的。我们讨论了一种静态方法来验证测试向量以节省宝贵的周期时间。两个设计的实验结果将被用来说明我们的方法。
ATPG tools generate test vectors assuming the zero delay model for logic gates. In reality, however, gates have finite rise and fall delays that are dependent on process, voltage, and temperature variations across different dies on a wafer and within a die. A test engineer must verify the vectors for timing correctness before they are handed off to the product engineer. Currently, validation of test vectors is done using dynamic simulation of the circuit using the test vectors. A test vector is invalidated if it cannot reliably distinguish between a good and a faulty circuit under the signal placement and observation error window of the tester equipment. As chips become faster, the need to test them at their intended speed of operation has been recognized; accordingly, at-speed functional tests, memory BIST, and transition delay tests are being used for modern ASICs. Since structural tests can result in much more switching activity in the circuit than what is estimated during normal functioning, they may fail delay testing due to nanometer effects such as crosstalk and IR drop. As a result, the validation performed by a dynamic simulation can be prone to error. Here is a case of a test that over-exercises the chip and declares it faulty even when the chip may work correctly in functional mode at the intended speed. One solution to this problem is to overdesign, e.g. oversize the power rails or increase wiring pitch, but this will impact the yield of the product. We propose layout-aware verification of at-speed test vectors and eliminating test vectors that can result in misclassification. Attempting to address this verification in dynamic simulation will force the use of circuit simulation or mixed-level simulation techniques, which are expensive in terms of run time. We discuss a static approach to validate the test vectors to save valuable cycle time. Experimental results on two designs will be presented to illustrate our approach.