Cloak: tolerating non-volatile cache read latency

Cloak: tolerating non-volatile cache read latency
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DOI:
10.1145/3524059.3532381
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发表时间:
2022-06
期刊:
Proceedings of the 36th ACM International Conference on Supercomputing
影响因子:
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通讯作者:
Apostolos Kokolis;Namrata Mantri;Shrikanth Ganapathy;J. Torrellas;J. Kalamatianos
Apostolos Kokolis;Namrata Mantri;Shrikanth Ganapathy;J. Torrellas;J. Kalamatianos
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其他
文献类型:
--
作者:
Apostolos Kokolis;Namrata Mantri;Shrikanth Ganapathy;J. Torrellas;J. Kalamatianos

文献摘要

相似文献

工作负载增加的内存需求给末级缓存(LLC)带来了很大压力。一般而言,由于底层SRAM技术的面积和功率要求,增加LLC容量的机会有限。有趣的是,新兴的非易失性存储器(NVM)技术由于其更高的面密度,有望成为LLC中SRAM的可行替代方案。但是,NVM的读写延迟要高得多,这抵消了它们在密度方面的优势。尽管研究人员已经提出了容忍NVM较高的写入延迟的方法,但很少强调关键的NVM读取延迟。为了解决这个问题,本文提出了Cloak。Cloak利用LLC中的页面级数据重用来隐藏NVM读取延迟。具体地说,对于某些L1 DTLB未命中,Cloak会将LLC驻留的数据从LLC NVM数组传输到一组小的SRAM页面缓冲区,这些SRAM页面缓冲区将服务于对该页面的后续请求。此外,为了实现页面行到页面缓冲区的高带宽、低延迟传输,Cloak使用了LLC布局,该布局可加速从页面发现LLC驻留的缓存行。我们通过在14个工作负载上对4核处理器进行全系统模拟来评估Cloak。我们发现,平均而言,安装了Cloak的机器比安装了SRAM LLC的机器快了23.8%,使用了仅支持NVM的LLC的机器快了8.9%-在这两种情况下,面积变化都可以忽略不计。此外,与这些设计相比,Cloak将ED2指标分别降低了39.9%和17.5%。
The increased memory demands of workloads are putting high pressure on Last Level Caches (LLCs). In general, there is limited opportunity to increase the capacity of LLCs due to the area and power requirements of the underlying SRAM technology. Interestingly, emerging Non-Volatile Memory (NVM) technologies promise a feasible alternative to SRAM for LLCs due to their higher area density. However, NVMs have substantially higher read and write latencies, which offset their density benefit. Although researchers have proposed methods to tolerate NVM's higher write latency, little emphasis has been placed on the critical NVM read latency. To address this problem, this paper proposes Cloak. Cloak exploits page-level data reuse in the LLC, to hide NVM read latency. Specifically, on certain L1 DTLB misses, Cloak transfers LLC-resident data belonging to the TLB-missing page from the LLC NVM array to a set of small SRAM Page Buffers that will service subsequent requests to this page. Further, to enable the high-bandwidth, low-latency transfer of lines of a page to the page buffers, Cloak uses an LLC layout that accelerates the discovery of LLC-resident cache lines from the page. We evaluate Cloak with full-system simulations of a 4-core processor across 14 workloads. We find that, on average, a machine with Cloak is faster than one with an SRAM LLC by 23.8% and one with an NVM-only LLC by 8.9%---in both cases, with negligible change in area. Further, Cloak reduces the ED2 metric relative to these designs by 39.9% and 17.5%, respectively.