An FPGA-based implementation of corner detection and matching with outlier rejection
An FPGA-based implementation of corner detection and matching with outlier rejection
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DOI：
10.1080/01431161.2018.1500728
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发表时间：
2018-08
影响因子：
3.4
通讯作者：
Jingjin Huang;Guoqing Zhou;Dianjun Zhang;Guangyun Zhang;Rongting Zhang;O. Baysal
中科院分区：
文献类型：
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作者：
Jingjin Huang;Guoqing Zhou;Dianjun Zhang;Guangyun Zhang;Rongting Zhang;O. Baysal
摘要为了满足亚像素精度的点对应的高帧速率要求，本文首先提出了一种现场可编程门阵列（FPGA）架构，包括角点检测，角点匹配，离群点拒绝，亚像素精度定位。该算法采用基于加速分段测试的特征（FAST）+二进制鲁棒独立基本特征（BRIEF）组合算法进行像素级精度的检测和匹配，采用基于斜率拒绝（SR）和基于相关系数拒绝（CCR）的组合算法剔除野值，采用基于梯度质心的算法进行亚像素级精度的定位。整个FPGA架构在单个FPGA平台（Xilinx XC 72 K325 T）上实现。五个图像数据集具有不同的空间分辨率，纹理，灯光，旋转角度，和视点被用来评估基于FPGA的实现的性能。实验结果表明：（1）SR和CCR算法能有效地剔除离群点;（2）对于覆盖人工纹理的图像对，其正确匹配率高于覆盖自然纹理的图像对;（3）该算法同样适用于光照、旋转角度和视点变化较小的图像对;（4）基于FPGA的实现速度可达每秒280帧（FPS），比基于个人计算机（PC）的实现速度快35倍;以及（5）对于所选FPGA平台，FPGA资源的使用是可接受的。当整个基于FPGA的实现进一步优化时，可以提高FPGA资源的速度和使用率。
ABSTRACT To meet the high frame rate requirements of correct point correspondences with a sub-pixel precision, this paper first proposes a Field Programmable Gate Array (FPGA) architecture that consists of corner detection, corner matching, outlier rejection, and sub-pixel precision localisation. In the architecture, a combined Features from Accelerated Segment Test (FAST)+ Binary Robust Independent Elementary Features (BRIEF) algorithm is adopted for detection and matching with pixel precision, a combined algorithm of Slope-based Rejection (SR) and Correlation-Coefficient-based Rejection (CCR) is used to reject the outliers, and a gradient centroid-based algorithm is used for sub-pixel precision localisation. The whole FPGA architecture is implemented on a single FPGA platform (Xilinx XC72K325T). Five image datasets with different spatial resolutions, textures, lights, rotate angles, and viewpoints are used to evaluate the performance of the FPGA-based implementation. The experimental results show that (1) the SR and CCR algorithms are effective for outlier rejection; (2) a higher correct matching rate is achieved for the image pairs that cover artificial textures than for those that cover natural textures; (3) the proposed architecture is also suitable for image pairs with small change of lights, rotate angles, and viewpoints; (4) the speed of the FPGA-based implementation can reach 280 Frames Per Second (FPS), which is 35 times faster than the Personal Computer (PC)-based implementation; and (5) the usage of FPGA resources is acceptable for the selected FPGA platform. The speed and usage of the FPGA resources can be improved when the whole FPGA-based implementation is further optimised.