A 390Mb/s 3.57mm2 3GPP-LTE turbo decoder ASIC in 0.13µm CMOS
A 390Mb/s 3.57mm2 3GPP-LTE turbo decoder ASIC in 0.13µm CMOS
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采用 0.13μm CMOS 的 390Mb/s 3.57mm2 3GPP-LTE Turbo 解码器 ASIC
DOI：
10.1109/isscc.2010.5433918
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发表时间：
2010
期刊：
影响因子：
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通讯作者：
Qiuting Huang
中科院分区：
文献类型：
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作者：
Christoph Studer;C. Benkeser;S. Belfanti;Qiuting Huang
智能手机、上网本以及其他移动宽带设备近期的流行，证明了3G（宽带码分多址/高速分组接入）作为主流高速数据使能技术的正确性，并为其4G后续技术——长期演进（LTE）带来了新的动力。由于预计在2到3年内进行大规模部署，开发具有成本效益且低功耗的LTE用户设备目前是无线行业关注的重点。虽然第一代终端的下行链路目标速率为100Mb/s，但基于多输入多输出（MIMO）的LTE标准能够以326.4Mb/s[1]的速率运行，这是高速下行分组接入（HSDPA）速率的20多倍。与HSDPA一样，Turbo译码（以及MIMO检测）将是计算强度方面的挑战之一，现在其计算强度可能会高出20倍。本文探讨了通过Turbo译码器专用集成电路（ASIC）实现达到LTE最大吞吐量的可行性，以及在具有竞争力的功耗和芯片面积的情况下实现100Mb/s这一里程碑的可行性。
Recent popularity of smart phones, netbooks, and other mobile broadband devices has vindicated 3G (WCDMA/HSPA) as an enabling technology for mainstream high-speed data and has given fresh impetus to its 4G successor, LTE (Long-Term Evolution). With mass deployment anticipated in 2-to-3 years, development of cost-effective and low-power LTE user equipment is currently keeping the wireless industry preoccupied. While the 1st-generation terminals will target 100Mb/s in the downlink, the MIMO-based LTE standard is capable of 326.4Mb/s [1] operation, which is more than 20× that of HSDPA. As with HSDPA, turbo decoding will be among the challenges (along with MIMO detection) in computation intensity, now threatening to be 20× higher. This contribution explores the feasibility of achieving the LTE maximum throughput with a turbo decoder ASIC realization, and the 100Mb/s milestone with competitive power consumption and die area.