Pseudo fail bit map generation for RAMs during component test and burn-in in a manufacturing environment
Pseudo fail bit map generation for RAMs during component test and burn-in in a manufacturing environment
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在制造环境中进行组件测试和老化期间为 RAM 生成伪故障位图
DOI：
10.1109/test.2001.966698
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发表时间：
2001
期刊：
影响因子：
--
通讯作者：
R. Rooney
中科院分区：
文献类型：
--
作者：
J. Vollrath;R. Rooney
在晶片测试期间在制造环境中产生半导体存储器的位故障图以识别工艺问题并用于修复。由于位失败映射功能对于高速测试器和大规模并行测试系统来说是昂贵的，因此组件测试仅生成通过/失败信息。很难将通过/未通过信息与过程问题联系起来。本文提出了一种测试策略和一个软件工具来构造伪位失败映射通过/失败信息使用一个特殊的测试序列。伪位故障图可以在制造环境中生成，并且可以用于识别过程问题并在故障位置处进行物理故障分析。
Bit fail maps of semiconductor memories are generated in a manufacturing environment during wafer test to identify process problems and for repair. Since bit fail map capabilities are expensive for high-speed testers and massive parallel test systems, component test is generating only pass/fail information. It is difficult to relate the pass/fail information to a process problem. This paper presents a test strategy and a software tool to construct pseudo bit fail maps from pass/fail information using a special test sequence. The pseudo bit fail map can be generated in a manufacturing environment and can be used for identifying process problems and doing physical failure analysis at the fail location.