A load-instruction unit for pipelined processors
A load-instruction unit for pipelined processors
复制标题
流水线处理器的加载指令单元
DOI：
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发表时间：
1993
影响因子：
1.3
通讯作者：
S. Vassiliadis
中科院分区：
文献类型：
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作者：
R. Eickemeyer;S. Vassiliadis
提出了特殊用途的负载单元作为处理器设计的一部分。该单元通过预先预测数据的地址提前获取数据。此预取允许在原本未使用的缓存周期中提早进行缓存访问，从而从负载指令中消除了一个周期。该预测还允许缓存数据在缓存中尚未进行预取数据。缓存失误的处理可以与其他指令执行重叠。使用痕量驱动的模拟显示，提出的机制在设计中纳入时可能会导致处理器性能的显着提高。本文还比较了不同的预测方法，并描述了负载单元的硬件实现。
A special-purpose load unit is proposed as part of a processor design. The unit prefetches data from the cache by predicting the address of the data fetch in advance. This prefetch allows the cache access to take place early, in an otherwise unused cache cycle, eliminating one cycle from the load instruction. The prediction also allows the cache to prefetch data if they are not already in the cache. The cache-miss handling can be overlapped with other instruction execution. It is shown, using trace-driven simulations, that the proposed mechanism, when incorporated in a design, may contribute to a significant increase in processor performance. The paper also compares different prediction methods and describes a hardware implementation for the load unit.