CoreSymphony: An Efficient Reconfigurable Multi-core Architecture
CoreSymphony: An Efficient Reconfigurable Multi-core Architecture
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CoreSymphony：高效的可重构多核架构
DOI：
10.1145/2082156.2082165
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发表时间：
2011
期刊：
影响因子：
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通讯作者：
Kenji Kise
中科院分区：
文献类型：
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作者：
Tomoyuki Nagatsuka;Yoshito Sakaguchi;Takayuki Matsumura;Kenji Kise
本文描述了一种协作式可重构的超标量处理器体系结构CoreSymphony，用于提高芯片多处理器中的单线程性能。CoreSymphony使一些窄问题核心能够融合到单个大问题核心中。在本文中，我们描述了实现协作式超标量处理器所涉及的问题。然后，我们描述克服这些问题的技术。使用SPEC2006基准获得的评估结果表明，四核融合实现的IPC比单个核高88%。
This paper describesCoreSymphony, a cooperative and reconfigurable superscalar processor architecture that improves single-thread performance in chip multiprocessor. CoreSymphony enables some narrow-issue cores to be fused into a single wide-issue core. In this paper, we describe the problems associated with achieving the cooperative superscalar processor. We then describe techniques by which to overcome these problems. The evaluation results obtained using SPEC2006 benchmarks indicate that four-core fusion achieves 88% higher IPC than an individual core.