An 8T/Cell FeFET-Based Nonvolatile SRAM with Improved Density and Sub-fJ Backup and Restore Energy
An 8T/Cell FeFET-Based Nonvolatile SRAM with Improved Density and Sub-fJ Backup and Restore Energy
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DOI：
10.1109/iscas48785.2022.9937438
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发表时间：
2022-05
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通讯作者：
Jianfeng Wang;Nuo Xiu;Juejian Wu;Yiming Chen;Yanan Sun;Huazhong Yang;N. Vijaykrishnan;Sumitha George;Xueqing Li
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文献类型：
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作者：
Jianfeng Wang;Nuo Xiu;Juejian Wu;Yiming Chen;Yanan Sun;Huazhong Yang;N. Vijaykrishnan;Sumitha George;Xueqing Li
在常关型瞬时开启应用中，嵌入式存储器的电源门控是防止长时间待机泄漏能量从而提高电源效率的一种有效方法。最近非易失性SRAM(NvSRAM)设计与单元内NVM元件备份的努力为正常模式计算和非模式备份和恢复(B&R)操作提供了一种有效的方法。对于这些努力，需要电路创新来实现B&R能量和面积开销之间的最佳平衡。在本文中，我们报告了一种新的基于8T/单元FeFET的nvSRAM设计，其性能优于以前基于FeFET的设计，具有更高的密度，同时仍然保持了每个B&R操作仅亚FJ能量的优势，比现有的基于RRAM的nvSRAM设计低363倍。与以前的基于FeFET的设计相比，该设计将每个单元的B&R晶体管数量从4个减少到仅2个，从而显著降低了11%的总面积开销。
In normally-off instant-on applications, power-gating of the embedded memory is an effective way for higher power efficiency by preventing long-standby-time leakage energy. Recent efforts of nonvolatile SRAM (nvSRAM) design with in-cell NVM element backup provide an efficient way for both normal-mode computing and off-mode backup and restore (B&R) operations. For these efforts, circuit innovations are required to achieve optimal balance between B&R energy and area overheads. In this paper, we report a novel 8T/cell FeFET-based nvSRAM design that outperforms prior FeFET-based designs with higher density, while still maintaining the advantage of only sub-fJ energy for each B&R operation, 363x lower than the existing RRAM-based nvSRAM design. Compared with prior FeFET-based designs, this design reduces the B&R transistor count per cell from 4 to only 2, which leads to a significant total area overhead reduction of 11%.