Optimal etch recipe prediction for 3D NAND structures
Optimal etch recipe prediction for 3D NAND structures
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3D NAND 结构的最佳蚀刻配方预测
DOI：
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发表时间：
2020
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通讯作者：
R. Bonnecaze
中科院分区：
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作者：
Leandro Medina;Bryan E. Sundahl;Meghali Chopra;R. Bonnecaze
我们提出了一种基于模型的实验设计方法，用于加速3D NAND结构上的演示的3D蚀刻优化。用于这种3D结构的蚀刻配方的设计和优化面临着重大挑战，需要昂贵且耗时的实验以实现所需的公差。3D NAND存储器器件还需要高纵横比沟槽和隔离狭缝的精确纳米加工，这对于在规范内可靠地制造是具有挑战性的。我们的模型有效地捕获了相关的物理和化学过程，这使得它们可以使用有限数量的实验样品进行校准，并且可以再现多层材料的真实3D蚀刻，包括弯曲，颈缩和锥形。由于我们的GPU驱动的模拟在几分钟内即可运行，因此可以在短时间内广泛探索相关的工艺参数空间。校准后的基于物理的模型可用于训练自适应的基于机器学习的算法，从而实现近乎即时的查询，例如用于数据可视化和分析。通过这种方法，我们展示了一种快速的方法，用于在蚀刻3D结构的工艺参数空间中定位最佳窗口。考虑的最优性度量包括对指定公差的符合性以及对过程参数变化的稳健性。这些技术可以降低复杂多层三维器件设计的成本和上市时间，并提高半导体器件产量。
We present a model-based experimental design methodology for accelerating 3D etch optimization with demonstration on 3D NAND structures. The design and optimization of etch recipes for such 3D structures face significant challenges requiring costly and time-consuming experiments in order to achieve the required tolerances. 3D NAND memory devices additionally require accurate nanofabrication of high aspect ratio trenches and isolation slits, which are challenging to manufacture reliably within specifications. Our model efficiently captures the relevant physical and chemical processes, which allows them to be calibrated using a limited number of experimental samples and can reproduce realistic 3D etch of multilayer materials, including bowing, necking, and tapering. Since our GPU-powered simulations run in a matter of minutes, the relevant process parameter space can be explored extensively in a short amount of time. The calibrated physics-based model can be used to train adaptive machine-learning-based heuristics which enable near-instant queries, for example for data visualization and analytics. With this approach, we show a rapid methodology for locating optimal windows in the process parameter space for etching 3D structures. Optimality metrics under consideration include both conformances to specified tolerances as well as robustness against process parameter variations. These techniques can reduce cost and time to market for complex multi-layer three-dimensional device designs and improve semiconductor device yields.