Solar intensity X-ray spectrometer (SIXS) ASIC for a large dynamic range onboard BepiColombo ESA mission to Mercury
Solar intensity X-ray spectrometer (SIXS) ASIC for a large dynamic range onboard BepiColombo ESA mission to Mercury
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太阳强度 X 射线光谱仪 (SIXS) ASIC，用于 BepiColombo ESA 水星任务中的大动态范围
DOI：
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发表时间：
2007
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通讯作者：
J. Huovelin
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作者：
F. Khalid;M. Prydderch;Q. Morrissey;P. Seller;E. Valtonen;J. Peltonen;M. Anttila;A. Malkki;R. Vainio;J. Huovelin
SIXS 仪器设计用于探测和测量 BepiColombo 水星轨道上的太阳 X 射线和太阳高能粒子。粒子探测器由一个CsI(Tl)核心探测器和5个GaAs表面探测器组成。粒子探测器的前端电子器件采用 ASIC 实现，需要 2,000e- 至 1,500,000e- 的大动态范围，并且在 -30°C 至 +55°C 的温度范围内积分非线性 (INL) < 3%。SIXS ASIC 测试结构的制造目的是确定差分与单端设计在噪声、电源抑制和电流消耗方面的性能。该 ASIC 有 8 个通道，每个通道由一个前置放大器、一个 CR-RC 整形器、一个峰值保持器、一个比较器和一个缓冲器组成，所有这些都使用封闭式几何晶体管设计。 GaAs 探测器有 6 个通道，具有 3 种不同的前置放大器类型，其中包括带零极点补偿的单端放大器；单端无极点零补偿和差分配置。 Csl 探测器有 2 个通道，采用单端和差分前置放大器设计。该 ASIC 采用 0.35 µm CMOS 工艺制造。描述了 ASIC 架构和设计流程，包括仿真和测量结果。
The SIXS instrument is designed for detecting and measuring solar X-rays and solar energetic particles in a Mercury orbit onboard BepiColombo. The particle detector consists of a CsI(Tl) core detector and 5 GaAs surface detectors. The front-end electronics of the particle detector is implemented as an ASIC which requires a large dynamic range of 2,000e- to 1,500,000e- and an integral non-linearity (INL) < 3% for a temperature range of -30deg C to +55deg C. The SIXS ASIC test structure has been manufactured to determine performance of differential vs. single-ended designs for noise, power supply rejection and current consumption. The ASIC has 8 channels, each of which consists of a preamplifier, a CR-RC shaper, a peak hold, a comparator and a buffer, all designed using enclosed geometry transistors. There are 6 channels for GaAs detectors with 3 different preamplifier types consisting of a single-ended with pole zero compensation; single-ended without pole zero compensation and a differential configuration. There are 2 channels for Csl detectors with single- ended and differential preamplifier designs. This ASIC has been manufactured in a 0.35 mum CMOS process. The ASIC architecture and design flow are described including simulated and measured results.