A leakage-energy-reduction technique for highly-associative caches in embedded systems
A leakage-energy-reduction technique for highly-associative caches in embedded systems
复制标题
嵌入式系统中高关联高速缓存的泄漏能量减少技术
作者：
Akihito Sakanaka;Seiichirou Fujii;Toshinori Sato
在纳米尺度技术中，功耗成为微处理器设计的最重要约束之一。特别地，随着晶体管电源电压和阈值电压按比例缩小，即使当晶体管不切换时，泄漏能量消耗也增加。本文提出了一种简单的降低静态能量的技术。我们的方法的关键思想是允许高速缓存中的方式以不同的速度访问，并将不经常访问的数据放入缓慢的方式。我们使用双Vt技术来实现非均匀的组相联缓存，并提出了一个简单的替换策略，以减少平均访问延迟。在32路集相联高速缓存上的实验结果表明，该方法不会显著增加应用程序的执行时钟周期，并能显著降低静态能量，从而提高了能量延迟积.
Power consumption is becoming one of the most important constraints for microprocessor design in nanometer scale technologies. Especially, as the transistor supply voltage and threshold voltage are scaled down, leakage energy consumption is increased even when the transistor is not switching. This paper proposes a simple technique to reduce the static energy. The key idea of our approach is to allow the ways within a cache to be accessed at different speeds and to place infrequently accessed data into the slow ways. We use dual-Vt technique to realize the non-uniform set-associative cache, and propose a simple replacement policy to reduce average access latency. Experimental results on 32-way set-associative caches demonstrate that any severe increase in clock cycles to execute application programs is not observed and significant static energy reduction can be achieved, resulting in the improvement of energy-delay product.