Design of a super-pipelined Viterbi decoder
Design of a super-pipelined Viterbi decoder
复制标题
超流水线维特比译码器的设计
DOI：
10.1109/iscas.1999.777822
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发表时间：
1999
期刊：
影响因子：
--
通讯作者：
H. Tenhunen
中科院分区：
文献类型：
--
作者：
Lihong Jia;Yonghong Gao;J. Isoaho;H. Tenhunen
本文提出了一种新的维特比译码器的超流水线VLSI结构。这种结构能够以面积有效的方式实现高吞吐量，因此它是一种用于实现维特比解码器的有吸引力的结构，其中需要大的约束长度和高吞吐率。通过增加基本处理元件的数量，可以线性地增加吞吐量。其显著的优点是它的规则性和灵活性。在0.6 /spl μ/m3.3VCMOS工艺中设计了一个维特比译码器（R=1/2K =10），验证了该结构的良好性能。
This paper presents a novel super-pipelined VLSI architecture for Viterbi decoders. This architecture is capable of achieving high throughput in an area-efficient manner and hence it is an attractive architecture for implementing the Viterbi decoder where a large constraint length and high throughput rate are required. The throughput can be linearly increased by increasing the number of basic process elements. The notable advantage is its regularity and flexibility. A Viterbi decode (R=1/2 K=10) is designed in 0.6 /spl mu/m 3.3 V CMOS process to demonstrate the favourable performance of this new architecture.