Hybrid Spin-CMOS Polymorphic Logic Gate With Application in In-Memory Computing
Hybrid Spin-CMOS Polymorphic Logic Gate With Application in In-Memory Computing
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DOI：
10.1109/tmag.2019.2955626
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发表时间：
2020-01
影响因子：
2.1
通讯作者：
Shaahin Angizi;Zhezhi He;An Chen;Deliang Fan
中科院分区：
文献类型：
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作者：
Shaahin Angizi;Zhezhi He;An Chen;Deliang Fan
在本文中，我们首先提出一种使用新型5端磁畴壁移动器件的混合自旋 - CMOS多态逻辑门（HPLG）。所提出的HPLG能够通过配置施加的键来执行全套的1输入和2输入布尔逻辑函数（即非、与/与非、或/或非以及异或/同或）。我们进一步表明，我们所提出的HPLG可以成为一种有前途的硬件安全原语，通过逻辑锁定和多态转换来解决集成电路伪造或逆向工程问题。在一组ISCAS - 89、ITC - 99和洛桑联邦理工学院（EPFL）基准测试上的实验结果表明，与近期的非易失性逻辑和基于CMOS的设计相比，HPLG在功耗 - 延迟积（PDP）方面分别获得了高达51.4%和10%的平均性能提升。然后，我们利用该逻辑门实现一种新颖的内存处理架构（HPLG - PIM），以实现高度灵活、高效和安全的逻辑计算。该架构没有在对成本敏感的存储器中集成复杂的逻辑单元，而是采用一种对硬件友好的方法，通过结合可重构读出放大器和HPLG单元来实现多个操作数之间的复杂逻辑功能，从而进一步降低延迟和高能耗的数据移动。在三个社交网络数据集上运行的广泛使用的图处理任务的器件 - 架构协同仿真结果表明，与近期的电阻式随机存取存储器（ReRAM）加速器相比，能效大约提高了3.6倍，速度提高了5.3倍。此外，与近期的动态随机存取存储器（DRAM）内处理加速方法相比，HPLG - PIM实现了约4倍的能效提升和5.1倍的速度提升。
In this article, we initially present a hybrid spin-CMOS polymorphic logic gate (HPLG) using a novel 5-terminal magnetic domain wall motion device. The proposed HPLG is able to perform a full set of 1- and 2-input Boolean logic functions (i.e., NOT, AND/NAND, OR/NOR, and XOR/XNOR) by configuring the applied keys. We further show that our proposed HPLG could become a promising hardware security primitive to address IC counterfeiting or reverse engineering by logic locking and polymorphic transformation. The experimental results on a set of ISCAS-89, ITC-99, and École Polytechnique Fédérale de Lausanne (EPFL) benchmarks show that HPLG obtains up to 51.4% and 10% average performance improvements on the power-delay product (PDP) compared with recent non-volatile logic and CMOS-based designs, respectively. We then leverage this gate to realize a novel processing-in-memory architecture (HPLG-PIM) for highly flexible, efficient, and secure logic computation. Instead of integrating complex logic units in cost-sensitive memory, this architecture exploits a hardware-friendly approach to implement the complex logic functions between multiple operands combining a reconfigurable sense amplifier and an HPLG unit to reduce the latency and the power-hungry data movement further. The device-to-architecture co-simulation results for widely used graph processing tasks running on three social network data sets indicate roughly $3.6\times $ higher energy efficiency and $5.3\times $ speedup over recent resistive RAM (ReRAM) accelerators. In addition, an HPLG-PIM achieves $\sim 4\times $ higher energy efficiency and $5.1\times $ speedup over recent processing-in-DRAM acceleration methods.