Efficient Analog Circuits for Boolean Satisfiability
Efficient Analog Circuits for Boolean Satisfiability
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DOI：
10.1109/tvlsi.2017.2754192
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发表时间：
2016-06
影响因子：
2.8
通讯作者：
Xunzhao Yin;B. Sedighi;M. Varga;M. Ercsey-Ravasz;Z. Toroczkai;X. Hu
中科院分区：
文献类型：
--
作者：
Xunzhao Yin;B. Sedighi;M. Varga;M. Ercsey-Ravasz;Z. Toroczkai;X. Hu
非多项式（NP）完全问题的有效解决方案将使科学和工业都受益匪浅。然而，这些问题在基于冯·诺依曼体系结构的数字计算机上是棘手的，因此需要替代解决方案来解决这些问题。最近，一个确定性的，连续时间动力系统（CTDS）被提出[1]，以解决一个代表性的NP完全问题，布尔可满足性（SAT）。这个求解器显示多项式模拟时间复杂性，即使是最难的基准$k$ -SAT（$k \geq 3$）公式，但通过指数驱动的辅助变量的能源成本。本文提出了一种新的模拟硬件SAT求解器，AC-SAT，实现CTDS通过纳入新的，模拟电路设计思想。AC-SAT的目的是作为一个协处理器，并可编程处理不同的问题规范。它是特别有效的解决硬$k$ -SAT问题的情况下，是具有挑战性的算法在数字机器上运行。此外，凭借其模块化设计，AC-SAT可以很容易地扩展到解决更大规模的问题，而电路的大小与变量数量和子句数量的乘积呈线性增长。该电路基于32 nm CMOS工艺进行设计和仿真。仿真程序与集成电路重点（SPICE）的仿真结果显示，即使是最困难的3-SAT问题的加速因子~104，与最先进的SAT求解器在数字计算机上相比。例如，对于具有$N=50$变量和$M=212$子句的难题，在几纳秒到几百纳秒内找到解决方案。
Efficient solutions to nonpolynomial (NP)-complete problems would significantly benefit both science and industry. However, such problems are intractable on digital computers based on the von Neumann architecture, thus creating the need for alternative solutions to tackle such problems. Recently, a deterministic, continuous-time dynamical system (CTDS) was proposed [1] to solve a representative NP-complete problem, Boolean Satisfiability (SAT). This solver shows polynomial analog time-complexity on even the hardest benchmark $k$ -SAT ( $k \geq 3$ ) formulas, but at an energy cost through exponentially driven auxiliary variables. This paper presents a novel analog hardware SAT solver, AC-SAT, implementing the CTDS via incorporating novel, analog circuit design ideas. AC-SAT is intended to be used as a coprocessor and is programmable for handling different problem specifications. It is especially effective for solving hard $k$ -SAT problem instances that are challenging for algorithms running on digital machines. Furthermore, with its modular design, AC-SAT can readily be extended to solve larger size problems, while the size of the circuit grows linearly with the product of the number of variables and the number of clauses. The circuit is designed and simulated based on a 32-nm CMOS technology. Simulation Program with Integrated Circuit Emphasis (SPICE) simulation results show speedup factors of ~104 on even the hardest 3-SAT problems, when compared with a state-of-the-art SAT solver on digital computers. As an example, for hard problems with $N=50$ variables and $M=212$ clauses, solutions are found within from a few nanoseconds to a few hundred nanoseconds.