Improved algorithms for link-based non-tree clock networks for skew variability reduction
Improved algorithms for link-based non-tree clock networks for skew variability reduction
复制标题
改进了基于链路的非树时钟网络的算法，以减少偏差变异性
DOI：
10.1145/1055137.1055150
复制
发表时间：
2005
期刊：
影响因子：
--
通讯作者：
Jiang Hu
中科院分区：
文献类型：
--
作者：
A. Rajaram;D. Pan;Jiang Hu
在纳米VLSI技术中，诸如制造变化，电源噪声，温度等的变化效应变得非常重要。作为任何同步VLSI芯片中最重要的网之一，时钟分布网络（CDN）对这些变化特别敏感。最近提出的基于链路的非树[1]通过构造与时钟树相比对变化更容易耐受性的非树来解决了这一问题。尽管[1]中提出的两种算法在降低偏差可变性方面有效，但它们具有一些缺点，包括高复杂性，冗长的链接和整个时钟网络的不均匀链接分布。在本文中，我们提出了两种可以克服这些缺点的新算法。使用基于HSPICE的Monte Carlo模拟验证了所提出算法的有效性。实验结果表明，与[1]中现有算法的15％线长度增加相比，新算法能够达到相同或更好的偏斜降低，平均增加了5％的电线长度。此外，新算法的规模非常适合大时钟网络，即时钟网络越大，整体链接成本越少（我们拥有的最大基准的总成本少于2％）。
In the nanometer VLSI technology, the variation effects like manufacturing variation, power supply noise, temperature etc. become very significant. As one of the most vital nets in any synchronous VLSI chip, the Clock Distribution Network (CDN) is especially sensitive to these variations. Recently proposed link-based non-tree [1] addresses this problem by constructing a non-tree that is significantly more tolerant to variations when compared to a clock tree. Although the two algorithms proposed in [1] are effective in reducing the skew variability, they have a few drawbacks including high complexity, lengthy links and uneven link distribution across the clock network. In this paper, we propose two new algorithms that can overcome these disadvantages. The effectiveness of the proposed algorithms has been validated using HSPICE based Monte Carlo simulations. Experimental results show that the new algorithms are able to achieve the same or better skew reduction with an average of 5% wire length increase when compared to the 15% wire length increase of the existing algorithms in [1]. Moreover, the new algorithms scale extremely well to big clock networks, i.e., the bigger the clock network, the less overall link cost (less than 2% for the biggest benchmark we have).