The semantics of power and ARM multiprocessor machine code

The semantics of power and ARM multiprocessor machine code
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DOI：
10.1145/1481839.1481842
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发表时间：
2009-01
期刊：
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影响因子：
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通讯作者：
J. Alglave;A. Fox;Samin S. Ishtiaq;Magnus O. Myreen;Susmit Sarkar;Peter Sewell;Francesco Zappa Nardelli
J. Alglave;A. Fox;Samin S. Ishtiaq;Magnus O. Myreen;Susmit Sarkar;Peter Sewell;Francesco Zappa Nardelli
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文献类型：
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作者：
J. Alglave;A. Fox;Samin S. Ishtiaq;Magnus O. Myreen;Susmit Sarkar;Peter Sewell;Francesco Zappa Nardelli

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我们开发了一个严格的语义电源和ARM多处理器程序，包括其宽松的内存模型和合理的片段，他们的指令集的行为。语义在HOL证明助手中被机械化。这应该为这些弱一致架构的低级代码的非正式推理和正式验证提供了良好的基础，并且与我们的x86语义一起，为高级并发语言的设计和编译提供了良好的基础。
We develop a rigorous semantics for Power and ARM multiprocessor programs, including their relaxed memory model and the behaviour of reasonable fragments of their instruction sets. The semantics is mechanised in the HOL proof assistant. This should provide a good basis for informal reasoning and formal verification of low-level code for these weakly consistent architectures, and, together with our x86 semantics, for the design and compilation of high-level concurrent languages.