Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study
Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study
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具有可控极性的垂直堆叠硅纳米线晶体管：稳健性研究
DOI：
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发表时间：
2013
期刊：
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通讯作者：
G. Micheli
中科院分区：
文献类型：
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作者：
P. Gaillardon;H. Ghasemzadeh;G. Micheli
具有栅极全方位控制的垂直堆叠硅纳米线FET（SiNWFET）是FinFET的自然和最先进的扩展。在先进技术节点，由于沟道界面处的肖特基接触，器件显示出双极行为，即，该器件同时表现出n型和p型特性。当由独立的双门（DG）结构控制时，这种特性可以用于逻辑计算，因为它提供了内在的XOR运算。晶体管的静电掺杂抑制了在源极和漏极区域处进行掺杂剂注入的需要，这潜在地导致器件的较大的工艺变化免疫性。在本文中，我们提出了一种新的方法，技术计算机辅助设计（TCAD）模拟的基础上，使新兴设备的可变性的预测。该方法用于我们的DG-SiNWFET框架中，并表明其极性受静电控制的器件对某些参数的变化具有更好的抗扰性，例如截止电流的标准偏差小16倍。
Vertically-stacked Silicon NanoWire FETs (SiNWFETs) with gate-all-around control are the natural and most advanced extension of FinFETs. At advanced technology nodes, due to Schottky contacts at channel interfaces, devices show an ambipolar behavior, i.e., the device exhibits n- and p-type characteristics simultaneously. This property, when controlled by an independent Double-Gate (DG) structure, can be exploited for logic computation, as it provides intrinsic XOR operation. Electrostatic doping of the transistor suppresses the need for dopant implantation at the source and drain regions, which potentially leads to a larger process variations immunity of the devices. In this paper, we propose a novel method based on Technology Computer-Aided Design (TCAD) simulations, enabling the prediction of emerging devices variability. This method is used within our DG-SiNWFET framework and shows that devices, whose polarity is controlled electrostatically, present better immunity to variations for some of their parameters, such as the off-current with 16× less standard deviation.