Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques
Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques
复制标题
使用同时双 VDD 和尺寸确定技术来优化单粒子翻转鲁棒性的设计
DOI：
10.1145/1233501.1233542
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发表时间：
2006
期刊：
影响因子：
--
通讯作者：
K. Mohanram
中科院分区：
文献类型：
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作者：
M. Choudhury;Quming Zhou;K. Mohanram
描述了一种设计对单粒子翻转（SEU）具有鲁棒性的组合电路的优化算法。一个简单的，高精度的模型的SEU鲁棒性的逻辑门。该模型-在正项形式-集成到一个优化框架的基础上的设计空间探索的几何规划的性能和功率约束。针对70 nm工艺技术，使用同时双VDD和栅极尺寸调整技术进行设计优化的仿真结果证明了这种方法可以实现的折衷
An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustness of a logic gate is developed. This model - in posynomial form - is integrated with performance and power constraints into an optimization framework based on geometric programming for design space exploration. Simulation results for design optimization using simultaneous dual-VDD and gate sizing techniques for the 70 nm process technology demonstrate the tradeoffs that can be achieved with this approach