Complex event detection at wire speed with FPGAs
Complex event detection at wire speed with FPGAs
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DOI：
10.14778/1920841.1920926
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发表时间：
2010-09
影响因子：
2.5
通讯作者：
L. Woods;J. Teubner;G. Alonso
中科院分区：
文献类型：
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作者：
L. Woods;J. Teubner;G. Alonso
复杂事件检测是数据流处理的高级形式，其中仔细检查流以识别给定的事件模式。许多复杂事件处理（CEP）系统面临的挑战是能够评估大容量数据流上的事件模式，同时遵守实时约束。为了解决这个问题，在本文中，我们提出了一种基于硬件的复杂事件检测系统实现的现场可编程门阵列（FPGA）。通过将FPGA直接插入到网络接口和CPU之间的数据路径中，我们的解决方案可以以千兆线速检测复杂事件，具有恒定且完全可预测的延迟，与网络负载、数据包大小或数据分布无关。这是对基于CPU的系统的重大改进，也是一种架构方法，为将CPU的灵活性与FPGA的并行性和处理能力相结合的混合流引擎提供了有趣的机会。
Complex event detection is an advanced form of data stream processing where the stream(s) are scrutinized to identify given event patterns. The challenge for many complex event processing (CEP) systems is to be able to evaluate event patterns on high-volume data streams while adhering to real-time constraints. To solve this problem, in this paper we present a hardware-based complex event detection system implemented on field-programmable gate arrays (FPGAs). By inserting the FPGA directly into the data path between the network interface and the CPU, our solution can detect complex events at gigabit wire speed with constant and fully predictable latency, independently of network load, packet size, or data distribution. This is a significant improvement over CPU-based systems and an architectural approach that opens up interesting opportunities for hybrid stream engines that combine the flexibility of the CPU with the parallelism and processing power of FPGAs.