Design of low power pulsed flip-flop using sleep transistor scheme
Design of low power pulsed flip-flop using sleep transistor scheme
复制标题
采用休眠晶体管方案的低功耗脉冲触发器设计
DOI：
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发表时间：
2013
期刊：
影响因子：
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通讯作者：
S. Rajendar
中科院分区：
文献类型：
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作者：
G. M. Rao;S. Rajendar
本文提出了一种新颖的低功耗脉冲触发器（P-FF）设计，该设计采用休眠晶体管方案。为了提高亚90nm低时钟负载动态触发器的泄漏鲁棒性，提出了一种新的休眠晶体管方案。该方案在Synopsis HSPICE中使用CMOS 90nm技术文件实现。与传统的脉冲触发触发器相比，基于睡眠晶体管的P-FF设计具有最佳的功率延迟产品性能。在不影响整体性能的前提下，降低了平均功率和泄漏功率。
In this paper, a novel low power pulsed flip-flop (P-FF) design featuring a sleep transistor scheme is proposed. In order to improve the leakage robustness for sub-90nm low clock load dynamic flip-flops, a novel sleep transistor scheme is proposed. The scheme is implemented using CMOS 90nm technology file in Synopsis HSPICE. As compared to the conventional pulse triggered flip-flops, the proposed sleep transistor based P-FF design features best power-delay-product performance. The average power and leakage power is reduced without degrading the overall performance.