Overview of 3D NAND Flash and progress of split-page 3D vertical gate (3DVG) NAND architecture
Overview of 3D NAND Flash and progress of split-page 3D vertical gate (3DVG) NAND architecture
复制标题
3D NAND Flash概述及分页3D垂直栅(3DVG) NAND架构进展
DOI：
--
复制
发表时间：
2014
期刊：
影响因子：
--
通讯作者：
Chih
中科院分区：
文献类型：
--
作者：
P. Du;H. Lue;Y. Shih;K. Hsieh;Chih
本文概述了各种3D NAND闪存器件，并全面了解了3DVG架构。与传统的浮栅闪存器件相比，电荷俘获（CT）器件提供了更简单的3D工艺集成和更小的占地面积，因此自然适用于3D NAND。在各种3D NAND闪存架构中，垂直栅极（VG）架构提供了上级间距可扩展性并且非常有吸引力。然而，水平信道使得双绞线（BL）解码更加困难，因此需要创新。我们提出了一种具有扭曲BL（偶数/奇数方向相反的BL）的分页3D垂直门（3DVG），解决了VG NAND的解码困难。在这项工作中，设备的性能，挑战和解决方案的分页3DVG。出色的MLC/TLC存储窗口已成功展示。
This paper provides an overview of various 3D NAND Flash memory devices and a comprehensive understanding of 3DVG architectures. Compared with conventional floating gate Flash memory devices, charge-trapping (CT) devices provide much simpler 3D process integration with smaller footprint thus are naturally suitable for 3D NAND. Among various 3D NAND Flash architectures, vertical gate (VG) architecture provides superior pitch scalability and is very attractive. However, the horizontal channel makes bitline (BL) decoding more difficult so innovation is required. We proposed a split-page 3D vertical gate (3DVG) with twisted BLs (even/odd BLs in the opposite directions) that solves the decoding difficulty of VG NAND. In this work, device performance, challenges, and solutions of split-page 3DVG are addressed. Excellent MLC/TLC memory window is successfully demonstrated.