Circuit reliability simulation based on Verilog-A
Circuit reliability simulation based on Verilog-A
复制标题
基于Verilog-A的电路可靠性仿真
DOI：
10.1109/bmas.2007.4437525
复制
发表时间：
2007
期刊：
影响因子：
--
通讯作者：
M. Kole
中科院分区：
文献类型：
--
作者：
M. Kole
由于长期电路退化的可靠性问题的迭代仿真环境已经开发用于SPICE类仿真器。NBTI（负偏置温度不稳定性）退化效应的标准Verilog-A语言开发的模型可以使用这个可靠性模拟器。集成在设计环境中，使电路设计人员能够轻松访问可靠性仿真。
An iterative simulation environment for reliability problems due to long-term circuit degradation has been developed for use in SPICE-like simulators. A model developed for the NBTI (negative bias temperature instability) degradation effect in the standard Verilog-A language can be used with this reliability simulator. Integration in a design environment allows easy access to reliability simulation for the circuit designer.