Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder
Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder
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DOI：
10.1109/tvlsi.2018.2822278
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发表时间：
2018-04
影响因子：
2.8
通讯作者：
Ayad M. Dalloo;Ardalan Najafi;Alberto García-Ortiz
中科院分区：
文献类型：
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作者：
Ayad M. Dalloo;Ardalan Najafi;Alberto García-Ortiz
利用精度和硬件成本之间的权衡，对于提高集成系统的效率具有巨大的潜力。利用这一概念，在过去的十年里提出了许多近似加法器。尽管在概念上不同，但所有以前的体系结构都是通过特殊的和非系统的方法获得的。相反，这份简报概括并系统地优化了近似加法器的架构模板。该方法在精度和硬件成本方面优于以往的方法，称为优化的下部恒定或加法器。例如，用我们的新方法实现的8位近似加法器将均方误差提高了58.5%，同时与以前报道的最佳结构相比，成本降低了7.2%。
Exploiting the tradeoff between accuracy and hardware cost has a tremendous potential to improve the efficiency of integrated systems. Using this concept, numerous approximate adders have been proposed in the last ten years. Although conceptually different, all previous architectures have been obtained with an ad hoc and nonsystematic methodology. Instead, this brief generalizes and systematically optimizes an architectural template for approximate adders. The outcome, called optimized lower part constant-OR adder (LOCA), outperforms previous approaches in terms of accuracy and hardware cost. For example, an 8-bit approximate adder implemented with our new approach improves the mean squared error by 58.5%, while simultaneously reducing the cost by 7.2% with respect to the previously reported best architecture.