AUTOMATIC GENERATION OF SCHEDULED SYSTEMC MODELS OF EMBEDDED SYSTEMS FROM EXTENDED TASK GRAPHS

AUTOMATIC GENERATION OF SCHEDULED SYSTEMC MODELS OF EMBEDDED SYSTEMS FROM EXTENDED TASK GRAPHS
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根据扩展任务图自动生成嵌入式系统的调度系统模型

DOI:
10.1007/0-306-48734-9_17
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发表时间:
2003
期刊:
Journal of VLSI signal processing systems for signal, image and video technology
影响因子:
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通讯作者:
T. Trautmann
T. Trautmann
中科院分区:
--
文献类型:
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作者:
Stephan Klaus;S. Huss;T. Trautmann

文献摘要

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基于扩展任务图(extended Task Graph, eTG)的抽象规范和分配、绑定和调度信息,生成了分布式嵌入式系统的可调度和可执行的SystemC事务级模型(TLM)。因此,整个通信和运行时控制被自动生成,并且SystemC仿真内核允许对规范进行及时执行和定时验证。所提出的规范模型的另一个好处是接口的一致定义,它支持块的封装并允许IP核的重用,从而导致分布式嵌入式系统的分层规范。
Based on an abstract specification denoted as extended Task Graph (eTG) and allocation, binding, and scheduling information, a scheduled and executable SystemC transaction level model (TLM) of distributed embedded systems is generated. Therewith, the whole communication and run-time control is being automatically produced, and the SystemC simulation kernel allows a timely execution and timing validation of the specification. A further benefit of the proposed specification model is the consistent definition of interfaces, which supports the encapsulation of blocks and enables the reuse of IP cores, thus leading to a hierarchical specification of distributed embedded systems.