Uniprocessor performance enhancement through adaptive clock frequency control
Uniprocessor performance enhancement through adaptive clock frequency control
复制标题
通过自适应时钟频率控制增强单处理器性能
DOI：
10.1109/tc.2005.34
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发表时间：
2005
影响因子：
3.7
通讯作者：
A. Uht
中科院分区：
文献类型：
--
作者：
A. Uht
单处理器设计始终假设最坏情况的操作条件来设置操作时钟频率，从而设置性能。然而，通过实验可以在典型的操作条件下获得更高的性能，但是这种增加频率的操作可能会出现系统故障，从而导致数据丢失/损坏。此外，诸如手机/互联网浏览器中的移动CPU不适应它们当前的环境（变化的温度条件等），从而增加或减少操作频率以最大化性能和/或允许在极端条件下操作。我们提出了一种数字硬件设计技术，实现了自适应时钟频率性能增强的数字硬件；该技术可以调整到近似性能最大化。成本低且设计简单。实验评估了在现场可编程门阵列 (FPGA) 中实现的流水线单处理器中的此类设计。
Uniprocessor designs have always assumed worst-case operating conditions to set the operating clock frequency and, hence, performance. However, much more performance can be obtained under typical operating conditions through experimentation, but such increased frequency operation is subject to the possibility of system failure and, hence, data loss/corruption. Further, mobile CPUs such as those in cell phones/Internet browsers do not adapt to their current surroundings (varying temperature conditions, etc.) so as to increase or decrease operating frequency to maximize performance and/or allow operation under extreme conditions. We present a digital hardware design technique realizing adaptive clock-frequency performance-enhancing digital hardware; the technique can be tuned to approximate performance maximization. The cost is low and the design is straightforward. Experiments are presented evaluating such a design in a pipelined uniprocessor realized in a field programmable gate array (FPGA).