Fabrication of Adiabatic Quantum-Flux-Parametron Integrated Circuits Using an Automatic Placement Tool Based on Genetic Algorithms
Fabrication of Adiabatic Quantum-Flux-Parametron Integrated Circuits Using an Automatic Placement Tool Based on Genetic Algorithms
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使用基于遗传算法的自动布局工具制造绝热量子通量参量集成电路
DOI：
10.1109/tasc.2019.2900220
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发表时间：
2019
影响因子：
1.8
通讯作者：
Yoshikawa Nobuyuki
中科院分区：
文献类型：
--
作者：
Tanaka Tomoyuki;Ayala Christopher L.;Xu Qiuyun;Saito Ro;Yoshikawa Nobuyuki
绝热量子流参变（AQFP）逻辑是一种超导逻辑家族，与传统的快速单通量量子逻辑电路相比具有更高的能量效率。与最先进的CMOS技术相比，AQFP逻辑电路具有相对较快的时钟速度（5-10 GHz）和5 - 6个数量级的能量降低的优势，但它也存在一些挑战。一个问题是，当前用于AQFP集成电路设计的设计环境不足，特别是对于大规模电路。在没有合适的设计环境的情况下，大型AQFP集成电路的设计是非常复杂的过程，因为它是耗时的并且容易出现人为错误。为了改善大规模AQFP逻辑电路的设计流程，我们开发了一个工具，可以有效地将AQFP逻辑单元的芯片上使用进化计算。我们在三个不同的基准电路上执行此程序，并确认电路布局的结果质量变得更好。布线长度可以减少27.9%，这反过来又减少了12.7%的约瑟夫森结的数量，它们最初用于长线中继器的插入缓冲器。为了评估我们的工具可以生产制造就绪的设计，我们设计和制造的基准电路之一，即4位移位器旋转器使用我们开发的工具。我们确认部分操作。
Adiabatic quantum-flux-parametron (AQFP) logic is a kind of superconductor logic family that has higher energy efficiency compared to conventional rapid single-flux-quantum logic circuits. When compared to state-of-the-art CMOS technology, AQFP logic circuits have the advantage of relatively fast clock speeds (5-10 GHz) and five-six orders of magnitude reduction in energy, but it has some challenges. One problem is that the current design environment for AQFP integrated circuit design is insufficient, especially for large-scale circuits. Without a suitable design environment, the design of large AQFP integrated circuits is a very complicated process as it is time consuming and is prone to human error. To improve the design flow for large-scale AQFP logic circuits, we developed a tool that can efficiently place AQFP logic cells on a chip using evolutionary computation. We executed this program on three different benchmark circuits and confirm that the quality-of-results of the circuit placement becomes better. The wiring length can be reduced by up to 27.9%, which in turn reduces the number of Josephson junctions by 12.7%, from which they were originally used in inserted buffers for long-wire repeaters. To evaluate how well our tool can produce fabrication-ready designs, we designed and fabricated one of the benchmark circuits, namely a 4-bit shifter-rotator using our developed tool. We confirm partial operation.
用于 VLSI 单元放置的快速神经网络算法
DOI：
10.1016/s0893-6080(98)00089-6
发表时间：
1998
期刊：
Neural networks : the official journal of the International Neural Network Society
影响因子：
--
作者：
C. Aykanat;T. Bultan;Ismail Haritaoglu
通讯作者：
Ismail Haritaoglu
影响因子：
1.8
作者：
Manheimer, Marc A.
通讯作者：
Manheimer, Marc A.