High voltage devices - a milestone concept in power ICs
High voltage devices - a milestone concept in power ICs
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DOI：
10.1109/iedm.2004.1419185
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发表时间：
2004-12
期刊：
影响因子：
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通讯作者：
F. Udrea;T. Trajkovic;G. Amaratunga
中科院分区：
文献类型：
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作者：
F. Udrea;T. Trajkovic;G. Amaratunga
我们首次报告了功率集成电路中的技术概念。我们介绍了在几年的开发过程中获得的详细实验数据，并演示了新技术在一系列高效开关模式电源（SMPS）中的应用。该技术能够提供3倍以上的电流密度（30 A/cm/sup /），以及2到5倍于最先进的功率IC技术（如结隔离或绝缘体上硅）的开关速度（500khz，适用于650V额定器件）。新概念基于MEMS和CMOS SOI技术的融合，以提高功率器件的击穿能力并降低其输出电容。MEMS步骤完全兼容CMOS，包括在功率器件的漂移区选择性地进行背面深度反应离子蚀刻（DRIE），以实现超薄硅介电膜的多膜。
We report for the first time a technology concept in power ICs. We present detailed experimental data obtained during several years of development and demonstrate the application of the new technology in a range of highly efficient switch mode power supplies (SMPS). This technology is capable of delivering more than 3 times higher current density (30 A/cm/sup 2/), and two to five times the switching speed (500 kHz for 650V rated devices) of state-of-the-art power IC technologies such as junction-isolation or silicon-on-insulator. The new concept is based on merging of the MEMS and CMOS SOI technologies to increase the breakdown ability of the power device and reduce its output capacitance. The MEMS step is fully CMOS compatible and consists of a back-side deep reactive ion etching (DRIE) performed selectively in the drift region of the power device to realize multiple membranes of ultra-thin silicon-dielectric films.