Modeling and Scaling of a-Si:H and Poly-Si Thin Film Transistors
Modeling and Scaling of a-Si:H and Poly-Si Thin Film Transistors
复制标题
a-Si:H 和多晶硅薄膜晶体管的建模和缩放
DOI：
--
复制
发表时间：
1997
期刊：
影响因子：
--
通讯作者：
S. Theiss
中科院分区：
文献类型：
--
作者：
M. Shur;H. Slade;T. Ytterdal;L. Wang;Zheng Xu;M. Hack;K. Aflatooni;Y. Byun;Yong P. Chen;M. Froggatt;A. Krishnan;P. Mei;H. Meiling;B. Min;A. Nathan;S. Sherman;M. Stewart;S. Theiss
我们开发了氢化非晶硅 (a-Si:H) 和多晶硅 (poly-Si) 薄膜晶体管 (TFT) 的 SPICE 分析模型，可准确模拟所有工作状态，温度依赖于 150°C，并随器件尺寸缩放。这些模型已在 [1, 2] 中介绍。在这项工作中，我们将模型预测的电流-电压特性与不同代工厂制造的 TFT 的测量特性进行了比较。我们比较提取的设备参数，以评估模型的稳健性并确定合适的默认参数集。我们还使用这些模型来检查短沟道 TFT 器件缩放的影响。可以使用电路模拟器 AIM-Spice [3] 访问这些模型，该模拟器可从 http://nina.ecse.rpi.edu/aimspice 获取。
We have developed analytic SPICE models for hydrogenated amorphous silicon (a-Si:H) and polysilicon (poly-Si) thin film transistors (TFTs) which accurately model all regimes of operation, are temperature dependent to 150°C, and scale with device dimensions. These models have been presented in [1, 2]. In this work, we compare the current-voltage characteristics predicted by our models with the measured characteristics from TFTs fabricated at different foundries. We compare the extracted device parameters in order to evaluate the robustness of our models and to determine a suitable default parameter set. We also use the models to examine the effects of device scaling for short channel TFTs. The models can be accessed using the circuit simulator AIM-Spice [3], which is available at http://nina.ecse.rpi.edu/aimspice.