A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving
A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving
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DOI：
10.1109/jssc.2014.2332532
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发表时间：
2014-11-01
影响因子：
5.4
通讯作者：
Tanaka, Yasunori
中科院分区：
文献类型：
--
作者：
Kawai, Natsumi;Takayama, Shinichi;Tanaka, Yasunori
提出了一种极低功耗的拓扑压缩触发器(TCFF)。与传统FFS相比，在数据活跃度为0%的情况下，FF的功耗降低了75%。这一功率降低比率是迄今已报道的FF中最高的。这种简化是通过应用拓扑压缩方法实现的，即将逻辑上等效的晶体管合并到非传统锁存结构中。连接到时钟信号的晶体管数量非常少，只有三个，大大降低了功率，并且较小的总晶体管计数确保了与传统FF相同的单元面积。此外，全静态全摆幅操作使单元能够容忍电源电压和输入摆动变化。采用40 nm CMOS工艺的实验芯片设计表明，几乎所有传统的FF都可以用所提出的FF替代，同时保持相同的系统性能和版图面积。
An extremely low-power flip-flop (FF) named topologically-compressed flip-flop (TCFF) is proposed. As compared with conventional FFs, the FF reduces power dissipation by 75% at 0% data activity. This power reduction ratio is the highest among FFs that have been reported so far. The reduction is achieved by applying topological compression method, merger of logically equivalent transistors to an unconventional latch structure. The very small number of transistors, only three, connected to clock signal reduces the power drastically, and the smaller total transistor count assures the same cell area as conventional FFs. In addition, fully static full-swing operation makes the cell tolerant of supply voltage and input slew variation. An experimental chip design with 40 nm CMOS technology shows that almost all conventional FFs are replaceable with proposed FF while preserving the same system performance and layout area.