A Digital PLL With a Stochastic Time-to-Digital Converter
A Digital PLL With a Stochastic Time-to-Digital Converter
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DOI：
10.1109/tcsi.2008.2010109
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发表时间：
2006-06
期刊：
影响因子：
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通讯作者：
V. Kratyuk;P. Hanumolu;Kerem Ok;U. Moon;K. Mayaram
中科院分区：
文献类型：
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作者：
V. Kratyuk;P. Hanumolu;Kerem Ok;U. Moon;K. Mayaram
提出了一种新的双环数字锁相环（DPLL）结构。它采用了一个随机的时间数字转换器（STDC）和高频delta-sigma抖动，以实现宽PLL带宽和低抖动在同一时间。STDC利用一组锁存器的随机特性来实现高分辨率。一个原型DPLL测试芯片已在0.13妈妈CMOS工艺制造，具有0.7-1.7 GHz的振荡器调谐范围和6.9 ps的均方根抖动，并消耗17 mW下1.2 V电源，而在1.2 GHz的工作。
A new dual-loop digital phase-locked loop (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high-frequency delta-sigma dithering to achieve wide PLL bandwidth and low jitter at the same time. The STDC exploits the stochastic properties of a set of latches to achieve high resolution. A prototype DPLL test chip has been fabricated in a 0.13-mum CMOS process, features a 0.7-1.7-GHz oscillator tuning range and a 6.9-ps rms jitter, and consumes 17 mW under 1.2-V supply while operating at 1.2 GHz.