LADDER: Architecting Content and Location-aware Writes for Crossbar Resistive Memories
LADDER: Architecting Content and Location-aware Writes for Crossbar Resistive Memories
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DOI：
10.1145/3466752.3480054
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发表时间：
2021-10
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通讯作者：
Md Hafizul Islam Chowdhuryy;M. Rashed;Amro Awad;Rickard Ewetz;Fan Yao
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作者：
Md Hafizul Islam Chowdhuryy;M. Rashed;Amro Awad;Rickard Ewetz;Fan Yao
以交叉开关形式组织的电阻存储器（ReRAM）有望用于主存储器集成。在提供高单元密度的同时，基于交叉开关的 ReRAM 由于 IR 压降的不同影响而受到 RESET 操作的可变写入延迟要求的影响，这共同取决于交叉开关的数据模式和正在 RESET 的目标单元的位置。最坏情况下 RESET 延迟的加剧会严重限制系统性能。在本文中，我们提出了 LADDER，这是一种有效且低成本的处理器端框架，它通过利用内容和位置依赖性来执行可变延迟的写入。为了实现内容感知，LADDER 采用了一种新颖的方案，该方案在内存中维护每行数据模式（即 1 的数量）的元数据，并通过内存控制器执行高效的元数据管理和缓存。 LADDER 不需要对 ReRAM 芯片进行硬件更改。我们设计了多项优化措施，进一步提高 LADDER 的性能，包括消除陈旧内存块读取的 LRS 元数据估计、减少最坏情况 LRS 计数器值的行内位级移位，以及优化要维护的计数器数量的多粒度 LRS 元数据设计。我们使用 16 个单程序和多程序工作负载评估 LADDER 的功效。我们的结果表明，与基准方案相比，LADDER 的性能平均提高了 46%，与最先进的设计相比，性能提高了 33%。此外，与现有架构方案相比，LADDER平均实现了28.8%的动态内存节能，并且对设备寿命的影响不到3%。
Resistive memories (ReRAM) organized in the form of crossbars are promising for main memory integration. While offering high cell density, crossbar-based ReRAMs suffer from variable write latency requirement for RESET operations due to the varying impact of IR drop, which jointly depends on the data pattern of the crossbar and the location of target cells being RESET. The exacerbated worst-case RESET latencies can significantly limit system performance. In this paper, we propose LADDER, an effective and low-cost processor-side framework that performs writes with variable latency by exploiting both content and location dependencies. To enable content awareness, LADDER incorporates a novel scheme that maintains metadata for per-row data pattern (i.e., number of 1’s) in memory, and performs efficient metadata management and caching through the memory controller. LADDER does not require hardware changes to the ReRAM chip. We design several optimizations that further boost the performance of LADDER, including LRS-metadata estimation that eliminates stale memory block reads, intra-line bit-level shifting that reduces the worst-case LRS-counter values and multi-granularity LRS-metadata design that optimizes the number of counters to maintain. We evaluate the efficacy of LADDER using 16 single- and multi-programmed workloads. Our results show that LADDER exhibits on average 46% performance improvement as compared to a baseline scheme and up to 33% over state-of-the-art designs. Furthermore, LADDER achieves 28.8% average dynamic memory energy saving compared to the existing architecture schemes and has less than 3% impact on device lifetime.