FPGA architecture for multi-style asynchronous logic [full-adder example]
FPGA architecture for multi-style asynchronous logic [full-adder example]
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适用于多风格异步逻辑的 FPGA 架构 [全加器示例]
DOI：
10.1109/date.2005.159
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发表时间：
2005
期刊：
影响因子：
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通讯作者：
M. Renaudin
中科院分区：
文献类型：
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作者：
N. Huot;H. Dubreuil;L. Fesquet;M. Renaudin
本文提出了一种新颖的用于实现各种风格的异步逻辑的FPGA体系结构。其主要目标是打破致力于异步逻辑的FPGA体系结构和逻辑风格之间的依赖。描述了该体系结构的创新方面。此外，由于体系结构的通用性，该结构非常适合重新构建和调整，以适应进一步的异步逻辑发展。采用不同的逻辑风格实现了一个全加器，体现了结构的灵活性。
This paper presents a novel FPGA architecture for implementing various styles of asynchronous logic. The main objective is to break the dependency between the FPGA architecture, dedicated to asynchronous logic, and the logic style. The innovative aspects of the architecture are described. Moreover, the structure is well suited to be rebuilt and adapted to fit with further asynchronous logic evolutions, thanks to the architecture genericity. A full-adder was implemented in different styles of logic to show the architecture flexibility.