Sparse Matrix-Dense Matrix Multiplication on Heterogeneous CPU+FPGA Embedded System
Sparse Matrix-Dense Matrix Multiplication on Heterogeneous CPU+FPGA Embedded System
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DOI：
10.1145/3381427.3381428
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发表时间：
2020-01
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影响因子：
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通讯作者：
Mohammad Hosseinabady;J. Núñez-Yáñez
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文献类型：
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作者：
Mohammad Hosseinabady;J. Núñez-Yáñez
嵌入式智能正在成为工业、医疗保健和汽车等新应用的主要驱动因素。这些应用程序的主要特点是高计算需求、与环境的实时交互、安全性、低功耗和本地自治等。针对这些不同的特性，研究人员提出了异构多核嵌入式系统，包括cpu、gpu、fpga和asic。虽然每个计算元素都提供了一个独特的功能来支持应用程序的一个特征，但在运行应用程序时协作这些处理核心以获得最大性能是一个关键的挑战。本文考虑了多核CPU和FPGA在异构嵌入式系统中的协同使用，以提高稀疏矩阵运算的性能，这是降低机器学习技术，特别是深度卷积神经网络中推理复杂性的基本技术。实验结果表明，在异构CPU+FPGA嵌入式系统Xilinx Zynq MPSoC上协同执行稀疏矩阵-密集矩阵乘法运算，与仅使用FPGA作为加速器相比，运算性能可提高42%。
Embedded intelligence is becoming the primary driver for new applications in industry, healthcare, and automotive, to name a few. The main characteristics of these applications are high computational demand, real-time interaction with the environment, security, low power consumption, and local autonomy, among others. Addressing these diverse characteristics, researchers have proposed heterogeneous multicore embedded systems comprising CPUs, GPUs, FPGAs, and ASICs. Whereas each computing element provides a unique capability to enable one of the application characteristics, collaborating these processing cores in running an application to get the maximum performance is a crucial challenge. This paper considers the collaborative usage of a multicore CPU and an FPGA in a heterogeneous embedded system to improve the performance of sparse matrix operations, which have been essential techniques in reducing the inference complexity in machine learning techniques, especially deep convolutional neural networks. Experimental results show that the collaborative execution of sparse-matrix-dense-matrix multiplication on the Xilinx Zynq MPSoC, a heterogeneous CPU+FPGA embedded system, can improve the performance by a factor of up to 42% compared with just using the FPGA as an accelerator.