Field Plate Designs in All-GaN Cascode Heterojunction Field-Effect Transistors
Field Plate Designs in All-GaN Cascode Heterojunction Field-Effect Transistors
复制标题
DOI：
10.1109/ted.2019.2897602
复制
发表时间：
2019-02
影响因子：
3.1
通讯作者：
Sheng Jiang;Kean-Boon Lee;Zaffar H. Zaidi;M. Uren;Martin Kuball;P. Houston
中科院分区：
文献类型：
--
作者：
Sheng Jiang;Kean-Boon Lee;Zaffar H. Zaidi;M. Uren;Martin Kuball;P. Houston
为了解决传统GaN+Si共源共栅器件中存在的电容匹配和关断可控性问题，对不同源场板(FP)连接进行了比较。实验结果表明，源端连接FP的共源共栅器件可以显著抑制关断状态的节点间电压，从而最小化电容能量损失和降低节点间过电压应力。这归因于耗尽型共源共栅部分的漏源极电容与共源共栅节点处的总电容的比率减小。在E模级联部分增加了FP，以进一步抑制关断状态的节点间电压，并使器件受益。源极FP连接到增强模式栅极的共源共栅器件在关断期间通过栅极电阻具有改进的开关可控性，从而增强了漏极环路中的DV/DT抗扰性。
Different source field plate (FP) connections are compared for the all-GaN integrated cascode device to address the capacitance matching and turn-off controllability issues reported in the conventional GaN plus Si cascode. The experimental results suggest that the cascode device with an FP connected to the source terminal can significantly suppress the off-state internode voltage, leading to minimized capacitive energy loss and reduced overvoltage stress at the internode. This is attributed to the reduced ratio of the drain–source capacitance of the depletion mode cascode part to the total capacitance at the cascode internode. An additional FP on the E-mode cascode part is proposed to further suppress the off-state internode voltage and benefit the device. Cascode devices with the source FP connecting to the enhancement mode gate have an improved switching controllability via gate resistance during turn-off and hence enhanced dv/dt immunity in the drain loop.