6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology

6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology
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6.2 采用 65nm CMOS 技术的 60Gb/s 288mW NRZ 收发器,具有自适应均衡和波特率时钟及数据恢复功能

DOI:
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发表时间:
2017
期刊:
IEEE International Solid-State Circuits Conference
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通讯作者:
E. Alon
E. Alon
中科院分区:
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文献类型:
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作者:
Jaeduk Han;Yue Lu;Nicholas Sutardja;E. Alon

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对超高速收发器的需求持续爆炸式增长,而高速I/O标准的数据速率也相应增加,收发器可用的历史恒定甚至减少的功率预算推动这些设计变得非常节能。为了开始解决这一需求,最近发布的NRZ收发器在28-40nm CMOS工艺中具有1接头DFE和/或CTLE[1,2],工作速度高达56.5Gb/s,其损耗通道<20dB,能量效率范围为4.4至11.96pJ/b。为了支持具有更高损耗的信道,[3]中描述的半速率65nm接收器前端设计包括一个3抽头DFE,一个2抽头FFE和一个约2.88pJ/b的CTLE,但没有演示闭环均衡器自适应,也没有演示时钟和数据恢复。在这样的交错体系结构中,关闭这些循环尤为重要,因为在这些数据速率下,每个交错的数据路径可能导致明显不同的总体信道响应(ISI),对闭环CDR的需求是不言而喻的。因此,本文提出了一种完全自适应的60Gb/s收发器,支持>20dB信道损耗,采用65nm CMOS技术实现(图6.2.1)。全收发器(含波特率CDR)通过0.7m Twinax电缆实现60Gb/s和4.8pJ/b的能效。
The demand for ultra-high speed transceivers continues to explode, and while the data-rate for high-speed I/O standards has increased accordingly, the historically constant or even decreasing power budgets available for the transceivers push these designs to be extremely energy efficient. To begin addressing this need, recently published NRZ transceivers operating up to 56.5Gb/s with a 1-tap DFE and/or CTLE [1,2] in 28–40nm CMOS processes have been demonstrated for <20dB loss channels with energy efficiencies ranging from 4.4 to 11.96pJ/b. In order to support channels with higher losses, the half-rate 65nm receiver front-end design described in [3] includes a 3-tap DFE, a 2-tap FFE, and a CTLE at ∼2.88pJ/b, but neither closed-loop equalizer adaptation nor clock and data recovery were demonstrated. Closing these loops is especially critical in such an interleaved architecture, since at these data-rates each interleaved datapath can result in a noticeably different overall channel response (ISI), and the need for closed-loop CDR is self-evident. This paper therefore presents a fully adaptive 60Gb/s transceiver, supporting >20dB channel loss, implemented in a 65nm CMOS technology (Fig. 6.2.1). The full transceiver (including baud-rate CDR) achieves 60Gb/s and 4.8pJ/b energy efficiency over a 0.7m Twinax cable.