Ultralow Specific On-Resistance Superjunction Vertical DMOS With High-K Dielectric Pillar
Ultralow Specific On-Resistance Superjunction Vertical DMOS With High-K Dielectric Pillar
复制标题
具有高 k 电介质柱的超低比导通电阻超结垂直 DMOS
DOI：
10.1109/led.2012.2196969
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发表时间：
2012-07-01
影响因子：
4.9
通讯作者：
Li, Z. J.
中科院分区：
文献类型：
--
作者：
Luo, Xiaorong;Jiang, Y. H.;Li, Z. J.
提出并通过模拟研究了一种在沟槽栅极下方具有高 k (HK) 电介质柱的超结 (SJ) VDMOS。 HK电介质引起n柱的自适应辅助耗尽。这不仅增加了 n 柱掺杂浓度，从而降低了比导通电阻 (R-on,R-sp)，而且还缓解了 SJ 器件中的电荷不平衡问题。 HK电介质在高压阻断状态下削弱了横向场并增强了垂直场强度，从而提高了击穿电压（BV）。通过沟槽侧壁的离子注入形成窄且高掺杂的n柱，以进一步降低R-on、R-sp。与传统的 SJ VDMOS 相比，R-on,(sp) 降低了 42%，BV 提高了 15%。
A superjunction (SJ) VDMOS with a high-k (HK) dielectric pillar below the trench gate is proposed and investigated by simulation. The HK dielectric causes a self-adapted assistant depletion of the n pillar. This not only increases the n-pillar doping concentration and thus reduces the specific on-resistance (R-on,R-sp) but also alleviates the charge-imbalance issue in SJ devices. The HK dielectric weakens the lateral field and enhances the vertical field strength in a high-voltage blocking state, leading to an improved breakdown voltage (BV). Ion implantation through trench sidewalls forms narrow and highly doped n pillars to further reduce the R-on,R-sp. The R-on,(sp) decreases by 42%, and BV increases by 15% compared with those of a conventional SJ VDMOS.