DPReDO: Dynamic Partial Reconfiguration enabled Design Obfuscation for FPGA Security
DPReDO: Dynamic Partial Reconfiguration enabled Design Obfuscation for FPGA Security
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DOI：
10.1109/socc56010.2022.9908070
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发表时间：
2022-09
期刊：
影响因子：
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通讯作者：
Sandeep Sunkavilli;N. Chennagouni;Qiaoyan Yu
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文献类型：
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作者：
Sandeep Sunkavilli;N. Chennagouni;Qiaoyan Yu
FPGA的安全性正受到逆向工程、特洛伊木马和旁道分析攻击的挑战。尽管现有的静态混淆方法可以保护集成电路免受IP盗版和硬件篡改，但它们仍然容易受到FPGA中的持续攻击。在这项工作中，我们利用FPGA CAD工具的先进功能，开发了一个动态部分重配置启用设计混淆（DPReDO）的方法。FPGA仿真结果表明，对于每个混淆变量更新，所提出的动态混淆方法仅消耗现有静态混淆所需的FPGA重新配置时间的1.5%。我们的案例研究表明，我们的方法的网表合成时间比基线少26%。
FPGA security is being challenged by reverse engineering, Trojan, and side-channel analysis attacks. Although the existing static obfuscation methods can protect the integrated circuits from IP piracy and hardware tampering, they are still vulnerable to persistent attacks in FPGAs. In this work, we leverage the advanced function of FPGA CAD tools to develop a Dynamic Partial Reconfiguration enabled Design Obfuscation (DPReDO) method. FPGA emulation results show that, for each obfuscation variant update, the proposed dynamic obfuscation method only consumes 1.5% of the FPGA reconfiguration time required by an existing static obfuscation. Our case study shows that the netlist synthesis time of our method is 26% less than the baseline.