SEU tolerant SRAM cell
SEU tolerant SRAM cell
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DOI：
10.1109/isqed.2011.5770789
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发表时间：
2011-03
期刊：
影响因子：
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通讯作者：
Sudipta Sarkar;Anubhav Adak;Virendra Singh;K. Saluja;M. Fujita
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文献类型：
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作者：
Sudipta Sarkar;Anubhav Adak;Virendra Singh;K. Saluja;M. Fujita
现代集成电路需要仔细注意导致位翻转的软错误，这通常是由α粒子或中子撞击引起的。这些事件，也被称为单粒子翻转（SEU），对于未来的技术将变得更加严重。在本文中，我们提出了一种新的10 T单粒子翻转容忍SRAM单元设计。我们的SRAM单元的面积效率与以前的建议相比。仿真结果表明，所提出的单元是强大的，因为它不会翻转，即使是一个标准的6T SRAM单元的四倍的Qcrit的瞬态脉冲。
Modern integrated circuits require careful attention to the soft errors resulting into bit upsets, which are normally caused by alpha particle or neutron hits. These events, also referred to as single-event upsets (SEUs), will become more severe for future technologies. In this paper we propose a novel 10T SEU tolerant SRAM cell design. Our SRAM cell is area efficient in comparison with the earlier proposals. Simulation results show that the proposed cell is robust as it does not flip even for a transient pulse with four times the Qcrit of a standard 6T SRAM cell.